At a Glance
- Tasks: Lead verification efforts for cutting-edge FPGA designs using SystemVerilog and UVM.
- Company: Join Riverlane, a forward-thinking tech company in Cambridge.
- Benefits: Enjoy a competitive salary, comprehensive benefits, and performance bonuses.
- Other info: Hybrid work model with opportunities for professional growth.
- Why this job: Be at the forefront of technology and innovation in a dynamic environment.
- Qualifications: Expertise in SystemVerilog, UVM, and FPGA design verification required.
The predicted salary is between 90000 - 115000 £ per year.
Riverlane in Cambridge is looking for a Staff Verification Engineer to take ownership of verification across designs. This full-time, hybrid role offers a salary of £90,000 to £115,000, depending on experience, along with a comprehensive benefits package and bonus.
Successful candidates will have expertise in SystemVerilog and UVM, with experience in FPGA design verification. The opportunity is ideal for a proactive individual passionate about technology and innovation.
Staff Verification Engineer — FPGA Systems & UVM Lead employer: Riverlane
Riverlane is an exceptional employer located in the vibrant city of Cambridge, offering a dynamic work culture that fosters innovation and collaboration. With a strong focus on employee growth, we provide comprehensive benefits, competitive salaries, and opportunities for professional development, making it an ideal place for those passionate about technology and looking to make a meaningful impact in the field of FPGA systems.
