Senior Digital Design Engineer
Senior Digital Design Engineer

Senior Digital Design Engineer

Full-Time 70000 - 90000 £ / year (est.) Home office (partial)
Riverlane

At a Glance

  • Tasks: Design and develop cutting-edge quantum computing solutions with a talented team.
  • Company: Join Riverlane, the world leader in quantum error correction technology.
  • Benefits: Enjoy a competitive salary, bonuses, private medical insurance, and 28 days leave.
  • Other info: Diverse and inclusive work environment with excellent growth opportunities.
  • Why this job: Make a real impact on groundbreaking technology that will change the world.
  • Qualifications: Experience in digital design and a passion for learning and innovation.

The predicted salary is between 70000 - 90000 £ per year.

Cambridge, UK | Full-time | Permanent | Hybrid

Salary: £70,000 to £90,000 DOE + Bonus + Benefits

The salary range for this role is broad, as we are able to consider varying levels of experience. Any offer made will carefully take into account level of experience (including relevant industry experience), transferable relevant skills and previous relevant achievements. We will also consider part‑time applications for this role. Please indicate your preferred working schedule in your cover letter.

About Us

Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science, to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved. Riverlane is the world leader in QEC technology.

Key Responsibilities

  • Experience with System on Chip solutions, with at least one CPU and custom accelerators.
  • Large-scale, complex systems on FPGA/ASIC.
  • Proven capability to test, debug and improve complex systems.
  • Ability to convert product requirements into technical specifications to document and share your work.
  • A curious nature and a passion for learning and continuous improvement.
  • Excellent communication skills, with the ability to work both independently and collaboratively as part of a team.

Even better if you have:

  • Experience with ASIC environments.

What Can You Expect From Us

  • A comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and a contributory pension scheme.
  • Equity, so that our team can share in the long‑term success of Riverlane.
  • 28 days annual leave, plus bank holidays and enhanced family leave.
  • A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 20 different nationalities.
  • A learning environment that encourages individual, team and company growth and development, including a regular programme of learning events and training and conference budgets.

Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity. Women and other underrepresented groups may be less likely to apply for a role unless they meet all or nearly all of the requirements. If this applies to you, we still encourage you to apply – you may be a great fit, even if you don’t meet every single qualification. We’ll love hearing from you. If you need any adjustments made to the application or selection process so you can do your best, please let us know – we will be happy to help.

Senior Digital Design Engineer employer: Riverlane

Riverlane is an exceptional employer located in Cambridge, UK, offering a dynamic and inclusive work culture that fosters innovation and collaboration among experts from diverse fields. With a comprehensive benefits package, including competitive salaries, equity options, and generous leave policies, employees are encouraged to grow both personally and professionally through continuous learning opportunities. Join us in our mission to revolutionise quantum error correction and contribute to groundbreaking advancements that will shape the future.
Riverlane

Contact Detail:

Riverlane Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land Senior Digital Design Engineer

✨Network Like a Pro

Get out there and connect with people in the industry! Attend meetups, webinars, or even just grab a coffee with someone who works at Riverlane. Building relationships can open doors that a CV just can't.

✨Show Off Your Skills

When you get the chance to chat with potential employers, don’t hold back! Share your projects, experiences, and how you’ve tackled challenges in digital design. Let your passion for quantum error correction shine through!

✨Tailor Your Approach

Before any interview, do your homework on Riverlane and its mission. Tailor your answers to show how your skills align with their goals in QEC. This shows you’re not just another candidate; you’re genuinely interested in being part of their journey.

✨Apply Through Our Website

Don’t forget to apply directly through our website! It’s the best way to ensure your application gets seen by the right people. Plus, it shows you’re proactive and really want to be part of the Riverlane team.

We think you need these skills to ace Senior Digital Design Engineer

Quantum Error Correction (QEC)
System on Chip (SoC) design
FPGA/ASIC development
Testing and debugging complex systems
Technical specification documentation
Communication Skills
Team Collaboration
Curiosity and passion for learning
Continuous Improvement
Experience with ASIC environments

Some tips for your application 🫡

Tailor Your CV: Make sure your CV is tailored to the Senior Digital Design Engineer role. Highlight relevant experience and skills that match the job description, especially in areas like ASIC environments and complex systems.

Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you're passionate about quantum error correction and how your background makes you a great fit for Riverlane. Don’t forget to mention your preferred working schedule!

Showcase Your Achievements: When detailing your experience, focus on specific achievements that demonstrate your ability to test, debug, and improve complex systems. Numbers and results speak volumes, so include them where possible!

Apply Through Our Website: We encourage you to apply through our website for a smoother application process. It’s the best way for us to receive your application and ensures you don’t miss out on any important updates!

How to prepare for a job interview at Riverlane

✨Know Your Quantum Stuff

Make sure you brush up on quantum error correction and its applications. Riverlane is all about mastering QEC, so being able to discuss its significance and recent advancements will show your genuine interest and expertise in the field.

✨Showcase Your Technical Skills

Prepare to talk about your experience with System on Chip solutions, FPGA/ASIC systems, and any relevant projects you've worked on. Be ready to explain how you've tested, debugged, and improved complex systems in the past, as this will be crucial for the role.

✨Communicate Clearly

Excellent communication skills are a must! Practice explaining technical concepts in simple terms, as you'll need to collaborate with a diverse team. Being able to document and share your work effectively will also be key, so think of examples where you've done this.

✨Be Curious and Open to Learning

Riverlane values a curious nature and a passion for continuous improvement. Prepare to discuss how you've pursued learning opportunities in the past and how you plan to keep growing in your role. This will demonstrate that you're not just looking for a job, but a chance to contribute and evolve.

Senior Digital Design Engineer
Riverlane

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