- We have an exceptional opportunity for a Verification Engineer to join our talented team of hardware designers and embedded software engineers. Together, you'll deliver fully verified, high-performance, and trusted systems
- In this exciting role you'll have end-to-end visibility across the entire stack, owning every aspect of verification and shaping how quality and reliability are built into our cutting-edge technology. You do not need a background in quantum computing! You will learn this along the way
- Proactively work with designers and architects to define verification plans based on design specifications. You will take full ownership of detailed test strategies across block-level and system-level designs
- Develop and implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. You will implement self-testing, directed and random tests to ensure every part of the system performs flawlessly
- Maintain the health and evolution of the design verification environment, tracking of regressions, coverage metrics and bugs to ensure our systems meet the highest standards of quality and reliability
- Women and other underrepresented groups may be less likely to apply for a role unless they meet all or nearly all of the requirements. If this applies to you, we still encourage you to apply - you may be a great fit, even if you don't meet every single qualification. We'd love to hear from you
Benefits
- Equity so that our team can share in the long-term success of Riverlane
- 28 days annual leave plus bank holidays and enhanced family leave
- Private medical insurance, life insurance and a contributory pension scheme
- Exposure to different programming languages, such as C, C++ and PythonKnowledge of SystemVerilog assertion (SVA)A collaborative person with excellent communication skills, who actively shares (and listens to) constructive feedbackAbility to work effectively with ambiguity and changing requirementsFormal verification experienceDemonstrable commercial experience in functional verification, including ownership of verification planning and strategyProven experience of testbench design with verification frameworks like UVM/OVMExperience debugging across RTL, simulation, and hardwareA proactive person who can independently define the scope of work
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Verification Engineer in Cambridge employer: Riverlane
Riverlane is an exceptional employer located in Cambridge, UK, offering a dynamic and inclusive work environment that fosters collaboration among experts in quantum computing. With a strong commitment to employee growth, Riverlane provides comprehensive benefits, including equity options, generous annual leave, and a focus on continuous learning through training and conference opportunities. Join us to be part of groundbreaking research in quantum error correction while enjoying the flexibility of hybrid working arrangements.
