Senior Verification Engineer — FPGA/UVM, Hybrid Cambridge
Senior Verification Engineer — FPGA/UVM, Hybrid Cambridge

Senior Verification Engineer — FPGA/UVM, Hybrid Cambridge

Cambridge Full-Time 90000 - 115000 £ / year (est.) No home office possible
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At a Glance

  • Tasks: Lead verification for cutting-edge designs and develop high-performance testbenches.
  • Company: Leading quantum technology firm in Cambridge with a focus on innovation.
  • Benefits: Competitive salary, hybrid work model, and diverse talent encouragement.
  • Why this job: Join an innovative team and make a real impact in quantum technology.
  • Qualifications: Strong experience in SystemVerilog and UVM, with excellent collaboration skills.
  • Other info: Opportunity to define your work scope in a dynamic environment.

The predicted salary is between 90000 - 115000 £ per year.

A leading quantum technology firm in Cambridge seeks a Staff Verification Engineer to lead verification across various designs. You will own the strategy and development of testbenches, ensuring high performance in real-world conditions.

Ideal candidates have strong experience in SystemVerilog and UVM, can independently define work scope, and excel in collaborative environments.

The role offers a competitive salary of £90,000 to £115,000 plus benefits, in a hybrid setting, encouraging diverse talents from various fields. Apply now to join this innovative team.

Senior Verification Engineer — FPGA/UVM, Hybrid Cambridge employer: Riverlane

As a leading quantum technology firm in Cambridge, we pride ourselves on fostering an innovative and collaborative work culture that empowers our employees to excel. With competitive salaries and a comprehensive benefits package, we offer exceptional growth opportunities for professionals in the tech industry, all within a vibrant hybrid working environment that values diverse talents and perspectives. Join us to be part of a forward-thinking team dedicated to pushing the boundaries of technology.
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Contact Detail:

Riverlane Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land Senior Verification Engineer — FPGA/UVM, Hybrid Cambridge

Tip Number 1

Network like a pro! Reach out to your connections in the quantum tech space and let them know you're on the lookout for opportunities. A personal recommendation can go a long way in landing that dream role.

Tip Number 2

Prepare for those interviews by brushing up on your SystemVerilog and UVM skills. Practice explaining your past projects and how you tackled challenges, as this will show your expertise and problem-solving abilities.

Tip Number 3

Don’t just apply anywhere; focus on companies that align with your values and interests. Check out our website for roles that excite you, and tailor your approach to each one to stand out from the crowd.

Tip Number 4

Follow up after interviews! A quick thank-you email can keep you fresh in the interviewer's mind and shows your enthusiasm for the position. Plus, it’s a great chance to reiterate why you’re the perfect fit.

We think you need these skills to ace Senior Verification Engineer — FPGA/UVM, Hybrid Cambridge

Verification Engineering
SystemVerilog
UVM
Testbench Development
Performance Testing
Work Scope Definition
Collaboration Skills
Hybrid Work Environment

Some tips for your application 🫡

Tailor Your CV: Make sure your CV highlights your experience with SystemVerilog and UVM. We want to see how your skills align with the role, so don’t be shy about showcasing relevant projects or achievements!

Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re passionate about verification engineering and how you can contribute to our innovative team. Keep it concise but impactful!

Showcase Your Collaborative Spirit: Since we value teamwork, mention any experiences where you’ve successfully collaborated with others. Whether it’s leading a project or working in a diverse team, let us know how you thrive in a collaborative environment.

Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you don’t miss out on any important updates from our team!

How to prepare for a job interview at Riverlane

Know Your Stuff

Make sure you brush up on your SystemVerilog and UVM knowledge. Be ready to discuss specific projects where you've implemented these technologies, as well as any challenges you faced and how you overcame them.

Show Your Strategy Skills

Prepare to talk about how you would approach developing testbenches for various designs. Think about the strategies you've used in the past and be ready to explain your thought process clearly.

Collaboration is Key

Since this role requires working in a collaborative environment, think of examples where you've successfully worked with others. Highlight your communication skills and how you contribute to team dynamics.

Ask Insightful Questions

Prepare some thoughtful questions about the company's projects and future directions. This shows your genuine interest in the role and helps you assess if the company is the right fit for you.

Senior Verification Engineer — FPGA/UVM, Hybrid Cambridge
Riverlane
Location: Cambridge

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