Riverlane is seeking a Verification Engineer in Cambridge to own end-to-end verification and drive the quality of our hardware and embedded software stacks. You will design scalable testbenches using SystemVerilog, implement checkers, and develop reference models to ensure robust, reliable systems.
Collaboration with designers will be essential to define plans and improve coverage. You will work across block- and system-level designs, maintain the verification environment, and track regressions
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End-to-End Verification Engineer - SystemVerilog in Cambridge employer: Riverlane
Riverlane is an exceptional employer located in Cambridge, UK, offering a dynamic and inclusive work environment that fosters collaboration among experts in quantum computing. With a strong commitment to employee growth, Riverlane provides comprehensive benefits, including equity options, generous annual leave, and a focus on continuous learning through training and conference opportunities. Join us to be part of groundbreaking research in quantum error correction while enjoying the flexibility of hybrid working arrangements.
