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- Tasks: Lead verification for cutting-edge quantum technology and collaborate with top engineers.
- Company: Join Riverlane, a leader in quantum error correction and innovation.
- Benefits: Enjoy competitive salary, bonuses, private medical insurance, and equity options.
- Why this job: Make a real impact in the future of technology while learning about quantum computing.
- Qualifications: Strong skills in SystemVerilog, UVM, and FPGA design verification required.
- Other info: Diverse team environment with excellent growth opportunities and flexible working options.
The predicted salary is between 75000 - 100000 £ per year.
Overview
Cambridge, UK | Full-time | Permanent | Hybrid
£90,000 to £115,000 (DOE) + Bonus + Benefits
The salary range for this role is broad, as we are able to consider varying levels of experience. Any offer made will carefully take into account level of experience (including relevant industry experience), transferable relevant skills and previous relevant achievements. We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.
About us
Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science, to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, breakthroughs can never be achieved. Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent and passion. We recently raised $75 million to accelerate our cutting-edge R&D. We partner with many of the world’s leading quantum computing companies and governments to accelerate their path to utility-scale quantum computers. We’re making remarkable progress and growing fast. Join us!
About the role
As a Staff Verification Engineer at Riverlane, you will take ownership of verification across block, subsystem, and multi-FPGA system-level designs. Collaborating closely with hardware designers and embedded software engineers, you will deliver systems that are fully verified, high-performing, and trusted. With visibility across the entire stack, you will partner closely with the Lead Verification Engineer to define and deliver the verification strategy—from early design discussions through to full system-level validation—ensuring every part of our technology meets the highest standards of performance and reliability. You do not need a background in quantum computing! You will learn this along the way.
What you will do
- Own the strategy and execution for block-level, subsystem, and multi-FPGA system designs.
- Develop scalable UVM-based testbenches that push the boundaries of performance across multiple FPGAs and configurations, ensuring our systems behave flawlessly in real-world conditions.
- Drive verification efforts with a sharp focus on risk, coverage, and system-level behaviour, setting the bar for quality and establishing best practices that elevate the wider team.
- Make pragmatic trade-offs to maintain world-class quality, while keeping pace with innovation, directly shaping the reliability and impact of Riverlane’s cutting-edge technology.
What we need
- Strong hands-on expertise in SystemVerilog and UVM.
- Experience verifying complex FPGA designs and integrations.
- Proven ability to debug across RTL, simulation, and hardware.
- Ability to work effectively with ambiguity and changing requirements.
- Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy.
- Exposure to different programming languages, such as C, C++, and Python.
- A proactive person who can independently define the scope of work.
- A collaborative person with excellent communication skills, who actively shares (and listens to) constructive feedback.
Even better if you have…
- Formal verification experience.
- Experience mentoring junior verification engineers.
What can you expect from us
- A comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and a contributory pension scheme.
- Equity, so that our team can share in the long-term success of Riverlane.
- 28 days annual leave, plus bank holidays and enhanced family leave.
- A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 20 different nationalities.
- A learning environment that encourages individual, team and company growth and development, including a regular programme of learning events and training and conference budgets.
How to apply
Please upload a CV and covering letter by clicking Apply Now. Your covering letter should explain why you are applying for the job and what skills and experience you can bring to the role. We review CVs as we receive them and interview as soon as we have applications that look like a good match. We do not use closing dates. So, please apply as soon as possible to avoid missing out on this role.
If you have any queries, please contact jobs@riverlane.com.
Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity. Women and other underrepresented groups may be less likely to apply for a role unless they meet all or nearly all of the requirements. If this applies to you, we still encourage you to apply - you may be a great fit, even if you don’t meet every single qualification. We’d love to hear from you.
If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help.
Staff Verification Engineer in Cambridge employer: Riverlane Ltd
Contact Detail:
Riverlane Ltd Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Staff Verification Engineer in Cambridge
✨Tip Number 1
Network like a pro! Reach out to folks in the quantum computing space, especially those at Riverlane. A friendly chat can open doors and give you insights that a job description just can't.
✨Tip Number 2
Prepare for the interview by brushing up on SystemVerilog and UVM. Make sure you can talk about your past experiences with FPGA designs and how you've tackled challenges in verification. We want to see your passion shine through!
✨Tip Number 3
Show off your collaborative spirit! Riverlane values teamwork, so be ready to share examples of how you've worked with others to achieve great results. Communication is key, so let us know how you handle feedback too.
✨Tip Number 4
Don't forget to apply through our website! It’s the best way to ensure your application gets seen. Plus, we review CVs as they come in, so the sooner you apply, the better your chances!
We think you need these skills to ace Staff Verification Engineer in Cambridge
Some tips for your application 🫡
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Make sure to explain why you're excited about the Staff Verification Engineer role and how your skills align with what we're looking for. Be genuine and let your passion for the field come through.
Tailor Your CV: Don't just send a generic CV! Tailor it to highlight your experience with SystemVerilog, UVM, and any relevant FPGA designs. We want to see how your background makes you a perfect fit for our team at Riverlane.
Showcase Your Problem-Solving Skills: In your application, give examples of how you've tackled complex verification challenges in the past. We love seeing candidates who can think critically and adapt to changing requirements, so don't hold back!
Apply Early!: We review applications as they come in, so don’t wait until the last minute! Apply through our website as soon as you can to ensure you don’t miss out on this exciting opportunity with us at Riverlane.
How to prepare for a job interview at Riverlane Ltd
✨Know Your Stuff
Make sure you brush up on SystemVerilog and UVM before the interview. Be ready to discuss your hands-on experience with FPGA designs and how you've tackled verification challenges in the past. This will show that you're not just familiar with the concepts, but that you can apply them effectively.
✨Show Your Problem-Solving Skills
Prepare to share specific examples of how you've debugged complex systems across RTL, simulation, and hardware. Riverlane values a proactive approach, so think about times when you had to work through ambiguity or changing requirements and how you navigated those situations.
✨Communicate Clearly
Since collaboration is key in this role, practice articulating your thoughts clearly. Be ready to discuss how you've worked with hardware designers and software engineers in the past. Highlight your ability to give and receive constructive feedback, as this will demonstrate your teamwork skills.
✨Be Ready to Learn
Even if you don't have a background in quantum computing, express your enthusiasm for learning. Riverlane is looking for someone who can grow with the company, so share your willingness to dive into new technologies and how you've approached learning in previous roles.
