At a Glance
- Tasks: Develop and execute verification plans for cutting-edge quantum systems.
- Company: Join Riverlane, a leader in quantum error correction technology.
- Benefits: Enjoy competitive pay, bonuses, private medical insurance, and 28 days leave.
- Other info: Diverse team environment with excellent growth and learning opportunities.
- Why this job: Be part of groundbreaking tech that tackles humanity's biggest challenges.
- Qualifications: Degree in Engineering or Computer Science; familiarity with digital logic and HDL languages.
The predicted salary is between 60000 - 80000 £ per year.
About us
Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved. Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent and passion.
Having raised more than $125M in funding to date to accelerate our cutting-edge R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.
About the role
We have an exceptional opportunity for a Graduate Verification Engineer to join our talented team of hardware designers and embedded software engineers. Together, you’ll deliver fully verified, high-performance, and trusted systems. In this exciting role you'll have end-to-end visibility across the entire stack, owning different aspects of verification and shaping how quality and reliability are built into our cutting-edge technology. You do not need a background in quantum computing! You will learn this along the way.
What you will do - specific responsibilities:
- Help with developing and executing verification plans for hardware blocks in Quantum Error Correction Systems
- Learn and support the creation of testbenches using SystemVerilog and UVM
- Run simulations and perform debugging to resolve issues in collaboration with the design team
- Collaborate with multi-disciplinary teams to understand specifications and define verification strategies for Quantum Error Correction systems
- Learn and apply best practices in verification to make methodology improvements
What we need - Essential Skills/Experience:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Science or related discipline
- Understanding of Digital Logic Design
- Some familiarity with HDL languages (e.g. Verilog, SystemVerilog) and simulation tools
- Good communication and problem-solving skills
- Relevant academic projects/internships/work experience
- Exposure to scripting languages such as Python
- Understanding of Object-Oriented Programming
- Exposure to UVM
What can you expect from us
- A comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and a contributory pension scheme
- Equity, so that our team can share in the long-term success of Riverlane
- 28 days annual leave, plus bank holidays and enhanced family leave
- A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 20 different nationalities
- A learning environment that encourages individual, team and company growth and development, including a regular programme of learning events and training and conference budgets
How to apply
Please upload a CV and covering letter by clicking 'Apply'. Your covering letter should explain why you are applying for the job and what skills and experience you can bring to the role. We review CVs as we receive them and interview as soon as we have applications that look like a good match. We do not use closing dates. So, please apply as soon as possible to avoid missing out on this role.
Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity. Women and other underrepresented groups may be less likely to apply for a role unless they meet all or nearly all of the requirements. If this applies to you, we still encourage you to apply - you may be a great fit, even if you don’t meet every single qualification. If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help.
GDPR notice: Riverlane collects and processes personal data in accordance with applicable data protection laws. If you are a European Job Applicant see the privacy notice for further details.
Graduate Software Development Engineer in Test New Cambridge, UK employer: Riverlane Ltd
Riverlane Ltd is an exceptional employer located in the vibrant city of Cambridge, offering a dynamic and inclusive work culture that fosters innovation and collaboration. With a strong commitment to employee growth, Riverlane provides ample opportunities for professional development and engagement in cutting-edge open-source projects, making it an ideal place for those passionate about quantum computing and software development. The comprehensive benefits package further enhances the rewarding experience of working at Riverlane, where your contributions can make a significant impact in the tech community.
