A leading technology firm in Cambridge is looking for a Staff Verification Engineer.
You will take ownership of verification across block and multi-FPGA systems.
Collaborating with designers, you will ensure systems are high-performing and reliable.
Strong expertise in SystemVerilog and UVM is crucial as you drive verification efforts, maintaining world-class quality in a hybrid work environment.
The role offers a salary range of Β£90,000 to Β£115,000 plus bonuses and benefits.
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Contact Detail:
Riverlane Ltd Recruiting Team