At a Glance
- Tasks: Lead the design of cutting-edge analog circuits for high-performance computing.
- Company: Join a dynamic startup focused on revolutionising silicon technology with innovative chiplet designs.
- Benefits: Enjoy flexible work options, competitive salary, and opportunities for professional growth.
- Why this job: Be part of a mission-driven team that values creativity and collaboration in tech innovation.
- Qualifications: MS or PhD in Electrical Engineering with significant experience in analog design and IP management.
- Other info: Work closely with industry experts and external vendors to shape the future of computing.
The predicted salary is between 48000 - 72000 £ per year.
Join a well-funded startup as an analog engineer leading the designs for droop sensing, clocking, PLL, LDO, On-die VRs, and PMICs using the latest finfet technology nodes. Our mission is to reimagine silicon and disrupt the high-performance computing platforms with the RiscV based chiplet designs.
Responsibilities
- Responsible for design and spec development and design of analog blocks for advanced mixed-signal / analog circuits.
- Write detailed design specifications and will be in close collaboration with the system architect, circuit designers, and design verification engineers.
- Work on behavioral modeling of analog blocks and support design verification to ensure bug-free silicon.
- Lead development of analog blocks in collaboration with external vendors and lead integration, test plan, and characterization efforts.
Requirements
- Strong track record of architecting, developing, verifying, and validating complete silicon IPs.
- Deep understanding of bandgaps, bias, opamps, switched-cap circuits, LDOs, PLLs, feedback and compensation techniques, DCDC converters.
- In-depth knowledge and good understanding of analog design techniques.
- Experience in digital integration of analog IPs with chip level integration team.
- Experience in developing behavioral modeling is a plus.
- Experience in IP design management or vendor management is a plus.
- Strong device physics knowledge as it applies to analog IC design.
- Hands-on experience with IP lab characterization using spectrum analyzers, oscilloscopes, signal generators, etc.
- Experience in working with production test engineers to produce test plans and design for testability details.
- Excellent communication skills.
- Team player with an ability to encourage team members.
Education & Experience
- MS (preferred in EE) plus 8 years.
- PhD (preferred in EE) plus 5 years.
Analog Mixed Signal Design employer: Rival
Contact Detail:
Rival Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Analog Mixed Signal Design
✨Tip Number 1
Network with professionals in the analog mixed signal design field. Attend industry conferences, webinars, or local meetups to connect with potential colleagues and learn about the latest trends and technologies. This can help you gain insights into what companies like us are looking for in candidates.
✨Tip Number 2
Showcase your hands-on experience with IP lab characterisation tools. If you've worked with spectrum analyzers, oscilloscopes, or signal generators, be prepared to discuss specific projects where you applied these skills. This practical knowledge is highly valued in our team.
✨Tip Number 3
Familiarise yourself with RiscV architecture and chiplet designs. Understanding the specifics of our mission to disrupt high-performance computing platforms will give you an edge during discussions. It shows your genuine interest in our work and how you can contribute.
✨Tip Number 4
Prepare to discuss your experience in vendor management and collaboration with external teams. Highlight any successful projects where you led integration efforts or developed test plans. This demonstrates your ability to work effectively in a team-oriented environment, which is crucial for us.
We think you need these skills to ace Analog Mixed Signal Design
Some tips for your application 🫡
Understand the Role: Before applying, make sure you fully understand the responsibilities and requirements of the Analog Mixed Signal Design position. Familiarise yourself with key terms like droop sensing, PLL, and LDO to demonstrate your knowledge in your application.
Tailor Your CV: Customise your CV to highlight relevant experience in analog design, particularly focusing on your track record with silicon IPs and any hands-on experience with lab characterisation tools. Use specific examples that align with the job description.
Craft a Compelling Cover Letter: Write a cover letter that showcases your passion for the role and the company’s mission. Mention your experience with RiscV based chiplet designs and how your skills can contribute to their goal of disrupting high-performance computing platforms.
Highlight Team Collaboration: Since the role involves close collaboration with various teams, emphasise your teamwork skills in your application. Provide examples of past projects where you successfully worked with system architects or verification engineers to achieve project goals.
How to prepare for a job interview at Rival
✨Showcase Your Technical Expertise
Be prepared to discuss your experience with analog design techniques in detail. Highlight specific projects where you've worked on bandgaps, LDOs, or PLLs, and be ready to explain your design choices and the outcomes.
✨Demonstrate Collaboration Skills
Since the role involves close collaboration with system architects and verification engineers, share examples of how you've successfully worked in teams. Emphasise your ability to communicate complex ideas clearly and encourage team members.
✨Prepare for Behavioural Modelling Questions
Given that behavioural modelling is a plus for this position, brush up on your knowledge and be ready to discuss any relevant experience. If you have developed models before, be prepared to explain your approach and the tools you used.
✨Understand the Company’s Mission
Research the startup's mission to disrupt high-performance computing platforms. Be ready to articulate how your skills and experiences align with their goals, particularly in relation to RiscV based chiplet designs.