Senior ASIC Verification Engineer - SystemVerilog & UVM Lead

A leading semiconductor company located in the United Kingdom is seeking a Senior Design Verification Engineer to enhance its hardware development team. The successful candidate will ensure the functional correctness of complex ASIC designs using advanced verification methodologies. Responsibilities include developing verification plans, creating testbenches, and collaborating with team members to deliver high-quality solutions. Applicants should have strong skills in SystemVerilog, UVM, and digital design verification, along with excellent communication abilities. #J-18808-Ljbffr