Staff Design Verification Engineer

b Overview /b p In this role you will ensure functional correctness and robustness of complex digital and mixed-signal ASICs using advanced verification methodologies. You collaborate with architects, designers, and fellow verifiers to deliver high-quality silicon. You will create testbenches, write verification tests, and drive both block-level and full-chip verification, including regression and post-silicon validation. The position offers impact through process improvements and mentoring, within a mission-driven hardware team. You will work with cross-functional groups to shape robust verification strategies. /p b Pay / Benefits /b ul li remote work option /li li flexible and inclusive work environment /li li Employee Resource Groups /li /ul b Responsibilities /b ul li Develop and execute verification plans for complex mixed-signal ASICs /li li Create and maintain SystemVerilog/UVM testbenches /li li Write and debug tests for functionality, performance, and corner cases /li li Perform block-level and full-chip verification including simulation, coverage, and regression /li li Collaborate with design engineers to define verification requirements /li li Analyze and resolve verification and post-silicon issues /li li Mentor junior engineers and improve verification processes /li li Participate in code reviews and drive continuous improvement of verification practices /li li Manage and debug gate-level simulation (pre/post-layout, with/without SDF timing) /li /ul b Key requirements /b ul li Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field /li li 10+ years in digital and/or mixed-signal design verification /li li Proficiency in SystemVerilog, UVM, and simulation tools (Synopsys VCS, Cadence Xcelium) /li li Strong understanding of RTL design and ASIC development flows /li li Scripting skills (Python, Perl, Tcl) for automation /li li Familiarity with formal, assertion-based, and coverage-driven verification /li li Excellent problem-solving and attention to detail /li li Strong communication and teamwork abilities /li li Experience with version control and CI/CD workflows /li li Experience with other verification methodologies (e/eRM, hardware/software co-simulation) /li li Knowledge of standard protocols (AMBA, I2C) /li /ul ul li problem-solving /li li communication /li li teamwork /li li SystemVerilog /li li UVM /li li Synopsys VCS /li /ul