Responsibilities Algorithm implementation: Translate complex probabilistic algorithms from high-level models, such as pseudocode/Python/C++/MATLAB, into highly pipelined, resource-efficient FPGA RTL. RTL design from scratch: Design and implement custom digital logic using VHDL where off-the-shelf vendor IPs are insufficient, bottlenecked, or introduce latency. High-speed I/O integration: architect data acquisition pipelines interfacing with the analogue front end via ultra-fast ADCs and high-speed transceivers, as well as interfacing to high-throughput computer host architectures via PCIe and high-speed Ethernet. System architecture: Work closely with hardware and software engineers, the research team, and ASIC architects to develop the high-level system architecture. Verification
FPGA Engineer employer: Quantum Dice
As a leading innovator in the tech industry, we pride ourselves on fostering a collaborative and dynamic work environment that empowers our employees to excel. Our HaaS Program Lead role offers not only competitive benefits and opportunities for professional growth but also the chance to work at the forefront of hardware and cloud technology in a vibrant location. Join us to be part of a team that values creativity, encourages continuous learning, and is dedicated to delivering exceptional solutions for our enterprise customers.
