Quant Capital is partnering with a leading trading firm to hire ASIC/FPGA engineers for its ultra-low latency hardware team in London. You will own physical design and verification, shaping floorplanning, place-and-route, timing closure and power analysis for demanding trading applications.
The role suits engineers who started in RTL design and moved into physical implementation, with 4+ years in RTL and verification and experience using Synopsys or Cadence tools.
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Low-Latency ASIC Engineer – Physical Design & Verification employer: Quant Capital
At Quant Capital, we pride ourselves on being an exceptional employer, offering a dynamic and innovative work environment that mirrors the culture of leading tech giants like Facebook and Google. Our London office fosters a collaborative atmosphere where employees are encouraged to think critically and make impactful decisions, while also providing ample opportunities for professional growth and mastery of cutting-edge technology in the trading operations space. With a focus on employee well-being and a commitment to excellence, we ensure that our team members are equipped with the tools and support they need to thrive in their roles.
