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- Tasks: Ensure functional correctness and performance of complex digital ASIC designs.
- Company: Leading tech firm specialising in advanced semiconductor solutions.
- Benefits: Attractive salary, flexible working options, and opportunities for skill development.
- Why this job: Join a team pushing the boundaries of technology and innovation.
- Qualifications: 7+ years in SystemVerilog/UVM with strong digital logic design skills.
- Other info: Collaborative environment with potential for significant career advancement.
The predicted salary is between 48000 - 72000 £ per year.
Ensure the functional correctness, performance, and adherence to specifications for complex digital ASIC Core/IP designs. This role focuses on deep, unit, and core-level verification.
Responsibilities
- Develop comprehensive Core Verification Plans based on the unit's micro-architecture and design specification.
- Design and implement reusable, robust verification environments using System Verilog/UVM.
- Create and execute constrained-random and directed tests to achieve high functional and code coverage for the core unit.
- Analyze simulation results, debug complex failures, and collaborate with the design team to root-cause and fix issues.
- Develop and maintain scripts (Python/Perl) to enhance the verification flow and regression management.
Requirements
- SystemVerilog/UVM expertise is mandatory.
- At least 7 years of hands-on expertise.
- Strong grasp of digital logic design and verification methodologies.
- Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
- Proven ability to work autonomously and demonstrate technical confidence when engaging with, and providing constructive feedback to, FE RTL design teams and CPU/IP micro-architects.
- Proficiency with industry-standard EDA simulation and debug tools.
- Solid abilities in debugging and root-cause analysis.
- Experience with scripting (Python, Perl).
- Excellent written and verbal communication skills in English are required.
Significant Advantage
- Strong knowledge of CPU/Processor architectures (e.g., pipeline, cache, instruction sets, exceptions) like ARM, X86 or RISC-V, is highly beneficial for verifying processor cores or complex IP blocks.
ASIC Design Verification in London employer: Qualitest
Contact Detail:
Qualitest Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land ASIC Design Verification in London
✨Tip Number 1
Network like a pro! Reach out to folks in the ASIC design verification field on LinkedIn or at industry events. A friendly chat can lead to opportunities that aren’t even advertised yet.
✨Tip Number 2
Show off your skills! Create a portfolio showcasing your projects, especially those involving System Verilog/UVM. This gives potential employers a taste of what you can do and sets you apart from the crowd.
✨Tip Number 3
Prepare for interviews by brushing up on common technical questions related to digital logic design and verification methodologies. Practising with a friend can help you articulate your thoughts clearly and confidently.
✨Tip Number 4
Don’t forget to apply through our website! We’ve got some fantastic roles waiting for talented individuals like you. Plus, it’s a great way to ensure your application gets the attention it deserves.
We think you need these skills to ace ASIC Design Verification in London
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your experience with SystemVerilog/UVM and any relevant projects. We want to see how your skills match the job description, so don’t be shy about showcasing your expertise in digital logic design!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re passionate about ASIC design verification and how your background makes you a perfect fit for our team. Keep it engaging and personal – we love to see your personality!
Showcase Your Problem-Solving Skills: In your application, mention specific examples where you’ve debugged complex issues or improved verification flows. We’re looking for candidates who can demonstrate their technical confidence and ability to collaborate effectively with design teams.
Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it shows you’re keen on joining the StudySmarter family!
How to prepare for a job interview at Qualitest
✨Know Your ASIC Inside Out
Before the interview, make sure you thoroughly understand the functional correctness and performance aspects of ASIC designs. Brush up on your knowledge of digital logic design and verification methodologies, as well as the specific requirements mentioned in the job description.
✨Showcase Your Verification Skills
Be prepared to discuss your experience with System Verilog and UVM. Bring examples of how you've developed comprehensive Core Verification Plans and implemented robust verification environments. Highlight any specific projects where you achieved high functional and code coverage.
✨Debugging is Key
Expect questions about debugging complex failures. Prepare to share your approach to analysing simulation results and collaborating with design teams. Discuss any tools or techniques you’ve used for root-cause analysis, as this will demonstrate your technical confidence.
✨Scripting Savvy
Since scripting in Python or Perl is part of the role, be ready to talk about your experience in automating verification flows. If you have examples of scripts you've written to enhance regression management, definitely bring those up during the conversation.