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- Tasks: Ensure functional correctness and performance of complex digital ASIC designs.
- Company: Leading tech firm focused on innovative ASIC solutions.
- Benefits: Remote work, competitive salary, and opportunities for professional growth.
- Why this job: Join a dynamic team and make an impact in cutting-edge technology.
- Qualifications: Expertise in SystemVerilog/UVM and strong digital logic design skills.
- Other info: Collaborative environment with excellent career advancement potential.
The predicted salary is between 48000 - 72000 £ per year.
Ensure the functional correctness, performance, and adherence to specifications for complex digital ASIC Core/IP designs. This role focuses on deep, unit, and core-level verification.
Responsibilities
- Develop comprehensive Core Verification Plans based on the unit's micro-architecture and design specification.
- Architect and implement reusable, robust verification environments using SystemVerilog/UVM.
- Create and execute constrained-random and directed tests to achieve high functional and code coverage for the core unit.
- Analyze simulation results, debug complex failures, and collaborate with the design team to root-cause and fix issues.
- Develop and maintain scripts (Python/Perl) to enhance the verification flow and regression management.
Requirements
- SystemVerilog/UVM expertise is mandatory.
- At least 7 years of hands-on expertise.
- Strong grasp of digital logic design and verification methodologies.
- Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
- Proven ability to work autonomously and demonstrate technical confidence when engaging with, and providing constructive feedback to, FE RTL design teams and CPU/IP micro-architects.
- Project experience with ARM based ecosystem components M7, Coresight, NIC and other AMBA bus interconnects.
- Familiarity with AMBA bus protocols and SoC system debug infrastructure.
- Strong experience with micro-architecture, Verilog/SystemVerilog, Synthesis, timing constraints development, Lint, CDC checks.
- Understanding of SoC interfaces like QSPI, UART, GPIOs.
- Proficiency with industry-standard EDA simulation and debug tools.
- Solid abilities in debugging and root-cause analysis.
- Experience with scripting (Python, Perl).
- Excellent written and verbal communication skills in English are required.
ASIC Design Verification Engineer employer: Qualitest
Contact Detail:
Qualitest Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land ASIC Design Verification Engineer
✨Tip Number 1
Network like a pro! Reach out to your connections in the ASIC design world, attend relevant meetups or webinars, and don’t be shy about asking for introductions. We all know that sometimes it’s not just what you know, but who you know!
✨Tip Number 2
Show off your skills! Create a portfolio showcasing your projects, especially those involving SystemVerilog/UVM and digital verification. This can really set you apart and give potential employers a taste of what you can do.
✨Tip Number 3
Prepare for interviews by brushing up on common technical questions related to digital logic design and verification methodologies. We recommend doing mock interviews with friends or using online platforms to get comfortable with the format.
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, we love seeing candidates who are proactive about their job search!
We think you need these skills to ace ASIC Design Verification Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV is tailored to the ASIC Design Verification Engineer role. Highlight your experience with SystemVerilog/UVM and any relevant projects you've worked on. We want to see how your skills match what we're looking for!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you're passionate about digital verification and how your background makes you a great fit for our team. Keep it concise but impactful – we love a good story!
Showcase Your Technical Skills: Don’t forget to mention your hands-on experience with digital logic design and verification methodologies. We’re keen to see examples of how you've tackled complex verification challenges in the past, so be specific!
Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you don’t miss out on any important updates. Plus, it shows us you’re serious about joining StudySmarter!
How to prepare for a job interview at Qualitest
✨Know Your Stuff
Make sure you brush up on SystemVerilog and UVM, as these are crucial for the role. Be prepared to discuss your hands-on experience and any specific projects where you've implemented these technologies.
✨Showcase Your Problem-Solving Skills
Be ready to talk about complex failures you've debugged in the past. Use examples that highlight your analytical skills and how you collaborated with design teams to resolve issues.
✨Demonstrate Your Scripting Skills
Since scripting in Python or Perl is part of the job, have examples ready of how you've used scripts to enhance verification flows. Discuss any tools or frameworks you've developed that improved efficiency.
✨Communicate Clearly
Strong communication skills are a must. Practice explaining technical concepts in simple terms, as you'll need to provide constructive feedback to design teams. Clear communication can set you apart from other candidates.
