Senior Staff Design Verification Engineer - Qualcomm, Bristol or Cambridge, UK

Company Qualcomm Technologies International Ltd

Job Area Engineering Group, Engineering Group > ASICS Engineering

General Summary Qualcomm invents breakthrough technologies that transform how the world computes, connects, and communicates. Today, our inventions are the foundation for life‑changing products, experiences, and industries. Qualcomm’s Voice and Music group is a leading player in the wireless earbud, headset, and smart speaker market. We develop and deliver hardware, software and applications that bring together the very latest wireless and audio technologies to create industry‑leading audio voice and music products.

About the Role Senior Staff Design Verification Engineer – provide technical leadership and end‑to‑end ownership of verification for complex low‑power, mixed‑signal IPs and SoCs. Based in Bristol or Cambridge, this role is suited to an engineer with demonstrated impact beyond a single project or block. As a Senior Staff Design Verification Engineer, you will set verification direction, influence design and system decisions, and ensure delivery of robust, production‑quality silicon. You will work at the intersection of architecture, digital design, analog, firmware, and systems, and act as a technical reference point for both execution and methodology. This role requires a balance of hands‑on technical depth, strategic ownership, and people influence, with accountability for verification outcomes across programs.

Key Responsibilities:

• Own and drive verification strategy, test planning, and methodology for complex digital and mixed‑signal IPs and subsystems.
• Partner closely with system and architecture teams to shape requirements, identify verification risks early, and ensure alignment on quality goals.
• Lead verification planning and reviews to ensure functional completeness, coverage closure, and sign‑off readiness.
• Architect and evolve scalable, reusable verification environments supporting low‑power techniques and mixed‑signal designs.
• Define and implement complex, system‑level test scenarios that reproduce real‑world and silicon‑observed failures.
• Drive debug and root‑cause analysis of complex issues, from simulation through regression and power‑aware flows, tracking issues to closure.
• Own DV execution outcomes for assigned projects, ensuring predictable delivery, risk transparency, and driving high verification quality.
• Use a variety of EDA tools, automation, and workflows to increase verification efficiency and robustness.
• Mentor and coach engineers in stimulus creation, checkers, assertions, coverage models, and debug best practices.
• Act as a technical leader within the DV community, influencing standards, best practices, and knowledge sharing.
• Communicate clearly and credibly with senior technical leadership and cross‑functional stakeholders.
• Model a positive, inclusive, and ownership‑driven mindset, contributing to a strong and collaborative engineering culture.
• Bring energy and enthusiasm to solving complex problems as part of a diverse, multi‑site team.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Preferred Qualifications:

• Exposure to Mixed‑Signal, Low‑Power verification with SV real‑number models, V‑models.
• Expertise in HVL such as SystemVerilog and UVM.
• Experience with formal verification (Jasper, VC Formal).
• Experience with design best practices and HW/FW interfaces.
• Strong working knowledge of digital design and SoC architecture.
• Scripting in Perl, TCL, or Python.
• Gate‑Level Simulation and Debug – 0‑delay, timing‑annotated.
• Experience in low‑power aware verification.
• Debugging regression failures and tracking to closure through a bug‑tracking process.
• Exposure to SystemC/HLS flows will be a bonus.
• Knowledge of AI, e.g., LLMs, coding assistance, and evolved design verification methodology using AI.

Minimum Education Requirements:

• Bachelor's degree in Electrical/Electronic Engineering.

Other Qualifications:

• 12+ years industry experience.
• Track record in delivering low‑power design from concept to post‑silicon support.

Preferred Education Requirements:

• Masters – Computer Engineering, Masters – Computer Science, Masters – Electrical Engineering.

References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

EEO Statement Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑accommodations@qualcomm.com or call Qualcomm’s toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.