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- Tasks: Develop and maintain verification infrastructure while collaborating with design teams.
- Company: Join a cutting-edge company leading the RISC-V revolution in various high-impact industries.
- Benefits: Enjoy a flat structure, diverse workload, and excellent benefits including remote work options.
- Why this job: Be part of an innovative team making a difference in machine learning, aerospace, and automotive sectors.
- Qualifications: Strong skills in SystemVerilog and UVM, with experience in verification methodologies required.
- Other info: Experience with RISC-V architectures is a plus; apply for more details!
The predicted salary is between 48000 - 72000 £ per year.
Join an innovative, rapidly expanding company at the forefront of the RISC-V revolution developing IC that has high-impact applications across machine learning, aerospace and automotive. Flat structure with a highly diverse workload and excellent benefits.
Responsibilities:
- Develop and maintain verification infrastructure in collaboration with design teams and external partners.
- Define and implement detailed verification strategies and architectures to ensure product quality and performance.
- Manage functional and code coverage metrics to track and report progress.
- Troubleshoot, debug and resolve issues while maintaining quality tracking dashboards and automated regression tests.
Requirements:
- Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies.
- A solid understanding of mixed hardware/software verification approaches.
- Experience with RISC-V architectures is preferred.
- Proven ability to work effectively with design teams and external partners to achieve project goals.
Contact Detail:
Platform Recruitment Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Verification Engineer
✨Tip Number 1
Familiarise yourself with the latest developments in RISC-V architectures. This will not only help you understand the company's focus but also allow you to engage in meaningful conversations during interviews.
✨Tip Number 2
Network with professionals in the verification engineering field, especially those who have experience with SystemVerilog and UVM. Attend relevant meetups or online forums to build connections that could lead to referrals.
✨Tip Number 3
Prepare to discuss your previous projects that involved verification strategies and methodologies. Be ready to explain how you tackled challenges and collaborated with design teams, as this will demonstrate your hands-on experience.
✨Tip Number 4
Showcase your problem-solving skills by preparing examples of how you've debugged and resolved issues in past roles. Highlighting your ability to maintain quality tracking dashboards and automated tests will set you apart.
We think you need these skills to ace Verification Engineer
Some tips for your application 🫡
Understand the Role: Before applying, make sure you fully understand the responsibilities and requirements of a Verification Engineer. Familiarise yourself with SystemVerilog, UVM, and RISC-V architectures to tailor your application accordingly.
Highlight Relevant Experience: In your CV and cover letter, emphasise your experience with verification methodologies and any projects where you've collaborated with design teams. Use specific examples to demonstrate your skills in troubleshooting and managing verification metrics.
Craft a Tailored Cover Letter: Write a compelling cover letter that connects your background to the job description. Mention your proficiency in SystemVerilog and UVM, and how your experience aligns with the company's focus on machine learning, aerospace, and automotive applications.
Proofread Your Application: Before submitting, carefully proofread your application materials for any errors or inconsistencies. A well-presented application reflects your attention to detail, which is crucial for a Verification Engineer.
How to prepare for a job interview at Platform Recruitment
✨Showcase Your Technical Skills
Make sure to highlight your proficiency in SystemVerilog and UVM during the interview. Be prepared to discuss specific projects where you've applied these skills, as well as any experience you have with mixed hardware/software verification approaches.
✨Understand RISC-V Architectures
If you have experience with RISC-V architectures, be ready to talk about it. If not, do some research beforehand to understand its significance in the industry and how it relates to the company's work.
✨Demonstrate Collaboration Skills
Since the role involves working closely with design teams and external partners, be prepared to share examples of how you've successfully collaborated in past projects. Highlight your communication skills and ability to manage relationships.
✨Prepare for Problem-Solving Questions
Expect questions that assess your troubleshooting and debugging abilities. Think of specific challenges you've faced in previous roles and how you resolved them, particularly in relation to maintaining quality tracking dashboards and automated regression tests.
