Platform Recruitment is seeking a Senior FPGA Engineer in Cambridge to oversee RTL design on ultra-low-latency platforms. You will architect RTL on high-end FPGAs, drive verification environments, and collaborate with firmware, software and infrastructure teams to optimise full-stack performance.
Required 7+ years FPGA/RTL experience, SystemVerilog, and hands-on with Vivado or Quartus. Familiarity with AXI/PCIe/Ethernet interfaces is preferred.
#J-18808-Ljbffr
Senior FPGA Architect: Ultra-Low Latency Systems in Cambridge employer: Platform Recruitment
As a leading employer in the graphics and engineering computing sector, we offer an innovative work culture that fosters collaboration and creativity. Our commitment to employee growth is evident through tailored development programmes and opportunities to lead impactful projects, making this role not just a job, but a pathway to a rewarding career. Located in a vibrant tech hub, our team enjoys a dynamic environment with access to cutting-edge resources and a supportive community.
