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Senior / Staff / Principal Analog Design Engineer - PLL

Senior / Staff / Principal Analog Design Engineer - PLL

London Full-Time 60000 - 84000 ÂŁ / year (est.) No home office possible
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At a Glance

  • Tasks: Design and develop cutting-edge analog systems for AI applications.
  • Company: Flux Computing creates innovative optical processors for advanced AI model training.
  • Benefits: Enjoy a dynamic work environment with exciting benefits and opportunities for growth.
  • Why this job: Join a passionate team pushing the limits of technology in a fast-paced setting.
  • Qualifications: 7+ years in CMOS design; strong problem-solving and collaboration skills required.
  • Other info: Frequent travel between Austin and London offices; ideal for tech enthusiasts.

The predicted salary is between 60000 - 84000 ÂŁ per year.

Join to apply for the Senior / Staff / Principal Analog Design Engineer – PLL role at Flux Computing

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Join to apply for the Senior / Staff / Principal Analog Design Engineer – PLL role at Flux Computing

Flux Computing designs and manufactures optical processors to train and run inference on large AI models. Join us to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed.
The Role
We’re searching for a Senior/Staff Analog Design Engineer with a strong focus on CMOS phase‑locked loops (PLLs) and clock‑distribution networks. You will architect, design and bring to production an ultra‑low‑jitter clocking subsystem that fans out precise multi‑GHz clocks to more than 100 parallel optical‑compute channels inside the OTPU. The work spans fractional‑N synthesisers, on‑chip loop filters, de‑skew circuits and high‑integrity clock‑tree distribution—all while meeting stringent power, spur and phase‑noise budgets required by next‑generation AI workloads.
Responsibilities

  • Architect, design and verify wide‑bandwidth fractional‑N PLLs (multi‑GHz output) including VCOs, charge pumps, loop filters and frequency dividers to achieve sub‑100 fs rms integrated jitter.

    • Develop clock‑distribution networks—buffer trees, deskew circuits, differential or CML fan‑outs—that deliver phase‑aligned clocks to > 100 destination blocks with < 5 ps channel‑to‑channel skew.

  • Co‑optimise the PLL with packaging, board, and power‑delivery teams to minimise supply‑induced jitter, crosstalk and electromagnetic coupling in a dense optical‑compute environment.
  • Create behavioural and transistor‑level models (Verilog‑A / SPICE) for system‑level co‑simulation of timing budgets, ensuring reliable link margins across PVT corners.
  • Drive post‑layout extraction, Monte‑Carlo analysis, and silicon bring‑up—including on‑wafer phase‑noise measurements, jitter transfer curves, and clock‑tree eye diagrams.
  • Mentor junior engineers, lead rigorous design reviews, and champion best‑practice methodologies for low‑jitter analog design and measurement.
  • Track and inject into the team the latest advances in PLL architectures, adaptive biasing, clock‑mesh techniques, and on‑chip jitter‑monitoring.

    • Skills & Experience

  • 7 + years of industry experience designing production CMOS PLLs, CDRs or other precision clock generators.

    • Demonstrated success achieving sub‑100 fs rms jitter and < –80 dBc reference‑spur performance at multi‑GHz frequencies.

  • Mastery of analog/RF EDA tools for schematic capture, SPICE‑/S‑parameter simulation, layout, parasitic extraction and mixed‑signal verification.
  • Deep understanding of phase‑noise theory, loop‑dynamics, supply‑noise coupling, clock‑tree deskew and electromagnetic crosstalk.
  • Bachelor’s degree in Electrical Engineering (or related); Master’s / PhD preferred.
  • Excellent problem‑solving, communication and cross‑disciplinary collaboration abilities.
  • Thrive in rapid‑iteration, high‑ownership environments; bring a portfolio of patents, publications or personal projects that showcases innovative clock‑generation or high‑speed analog design.

    • Frequent travel is expected between our Austin and London offices.
    We’re building fast and that includes our benefits. More exciting additions are coming soon for the Flux crew.
    If you are passionate about pushing the boundaries of what\’s possible in AI and thrive in a high-energy, fast-paced environment, we want to hear from you. Apply now to join Flux and be a key player in shaping the future of computing.

    Seniority level

    • Seniority level

      Mid-Senior level

    Employment type

    • Employment type

      Full-time

    Job function

    • Job function

      Engineering and Information Technology

    • Industries

      Semiconductor Manufacturing

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    Senior / Staff / Principal Analog Design Engineer - PLL employer: PageBolt WordPress

    At Flux Computing, we pride ourselves on being an exceptional employer, offering a dynamic work culture that fosters innovation and collaboration. Our team is dedicated to pushing the boundaries of AI technology, providing ample opportunities for professional growth and mentorship in a fast-paced environment. With competitive benefits and a commitment to employee well-being, working in our London office means being part of a cutting-edge company at the forefront of semiconductor manufacturing.
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    Contact Detail:

    PageBolt WordPress Recruiting Team

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    StudySmarter Expert Advice 🤫

    We think this is how you could land Senior / Staff / Principal Analog Design Engineer - PLL

    ✨Tip Number 1

    Network with professionals in the semiconductor and analog design fields. Attend industry conferences or local meetups to connect with potential colleagues at Flux Computing. Building relationships can often lead to referrals, which significantly increase your chances of landing an interview.

    ✨Tip Number 2

    Stay updated on the latest advancements in PLL architectures and clock distribution techniques. Follow relevant publications and join online forums where experts discuss innovations in analog design. This knowledge will not only prepare you for interviews but also demonstrate your passion for the field.

    ✨Tip Number 3

    Prepare to discuss your previous projects in detail, especially those that showcase your experience with CMOS PLLs and high-speed analog design. Be ready to explain your problem-solving approach and how you achieved specific performance metrics, as this will highlight your expertise during interviews.

    ✨Tip Number 4

    Familiarise yourself with Flux Computing's products and their applications in AI. Understanding their technology and how your skills can contribute to their goals will help you tailor your discussions and show that you're genuinely interested in being part of their team.

    We think you need these skills to ace Senior / Staff / Principal Analog Design Engineer - PLL

    CMOS Phase-Locked Loop (PLL) Design
    Clock Distribution Networks
    Ultra-Low Jitter Design
    Fractional-N Synthesizers
    On-Chip Loop Filters
    High-Integrity Clock-Tree Distribution
    Power and Phase Noise Budgeting
    Behavioural and Transistor-Level Modelling (Verilog-A / SPICE)
    Post-Layout Extraction
    Monte-Carlo Analysis
    Silicon Bring-Up
    Phase-Noise Measurement Techniques
    Jitter Transfer Curve Analysis
    Clock-Tree Eye Diagrams
    Mentoring and Leadership Skills
    Cross-Disciplinary Collaboration
    Analog/RF EDA Tools Proficiency
    Problem-Solving Skills
    Understanding of Phase-Noise Theory
    Supply-Noise Coupling Knowledge
    Electromagnetic Crosstalk Management

    Some tips for your application 🫡

    Tailor Your CV: Make sure your CV highlights your experience with CMOS PLLs and clock-distribution networks. Use specific examples from your past work that demonstrate your ability to achieve sub-100 fs rms jitter and your mastery of analog/RF EDA tools.

    Craft a Compelling Cover Letter: In your cover letter, express your passion for AI and how your skills align with the role at Flux Computing. Mention any relevant patents or publications that showcase your innovative contributions to high-speed analog design.

    Showcase Relevant Projects: Include a section in your application that details specific projects you've worked on related to PLL architectures or clock generation. Highlight your role, the challenges faced, and the outcomes achieved to demonstrate your problem-solving abilities.

    Highlight Collaboration Skills: Since the role involves mentoring junior engineers and collaborating across teams, emphasise your communication and teamwork skills. Provide examples of how you've successfully worked in cross-disciplinary environments in the past.

    How to prepare for a job interview at PageBolt WordPress

    ✨Showcase Your Technical Expertise

    Be prepared to discuss your experience with CMOS phase-locked loops (PLLs) and clock-distribution networks in detail. Highlight specific projects where you achieved sub-100 fs rms jitter and elaborate on the techniques you used to overcome challenges.

    ✨Demonstrate Problem-Solving Skills

    Expect technical questions that assess your problem-solving abilities. Prepare examples from your past work where you successfully tackled complex design issues, particularly in high-speed analog design or clock generation.

    ✨Familiarise Yourself with Latest Technologies

    Stay updated on the latest advances in PLL architectures and clock-mesh techniques. Being able to discuss recent innovations will show your passion for the field and your commitment to continuous learning.

    ✨Prepare for Collaborative Discussions

    Since the role involves cross-disciplinary collaboration, be ready to discuss how you've worked with packaging, board, and power-delivery teams in the past. Emphasise your communication skills and ability to mentor junior engineers.

    Senior / Staff / Principal Analog Design Engineer - PLL
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    • Senior / Staff / Principal Analog Design Engineer - PLL

      London
      Full-Time
      60000 - 84000 ÂŁ / year (est.)

      Application deadline: 2027-09-01

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