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- Tasks: Design and verify high-performance ASICs for cutting-edge AI applications.
- Company: Flux Computing creates innovative optical processors for AI model training and inference.
- Benefits: Enjoy competitive pay, remote work options, and exciting perks as part of a dynamic team.
- Why this job: Join a fast-paced environment where your work directly impacts the future of computing.
- Qualifications: 3+ years in digital ASIC/SoC design; mastery of SystemVerilog/UVM required.
- Other info: Frequent travel between Austin and London offices; mentorship opportunities available.
The predicted salary is between 72000 - 108000 ÂŁ per year.
Join to apply for the Digital Design Engineer – Verification role at Flux Computing
Join to apply for the Digital Design Engineer – Verification role at Flux Computing
Flux Computing designs and manufactures optical processors to train and run inference on large AI models. Join us to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed.
The Role
Weâre searching for a Digital Design Engineer who is passionate about building and verifying complex, highâperformance ASICs . You will own the definition and execution of verification strategies for the digital subsystems that control, configure and monitor Fluxâs optical datapaths and AI compute fabrics. Your work will ensure firstâsilicon success and robust, productionâworthy silicon that scales to dataâcentre volumes.
Responsibilities
- Architect, implement and maintain comprehensive verification environments (SystemVerilog + UVM, assertionâbased and formal) for datapath, control, memory and highâspeed I/O blocks in our OTPU.
- Define verification plans that target functional correctness, lowâpower modes, safety, reliability and security requirements; derive and track coverage metrics to closure.
- Develop reusable VIP and stimulus generators for modules such as networkâonâchip routers, DDR/LPDDR controllers, PCIe/CXL interfaces and proprietary photonic control logic.
- Collaborate closely with RTL designers to iterate on microâarchitectures, resolve cornerâcase bugs and balance PPA (power, performance, area) tradeâoffs uncovered during verification.
- Drive RTL quality â GDS signâoff: run lint, CDC/RDC, SDC constraint validation, gateâlevel simulations, GLS with SDF, and powerâaware checks; work with physicalâdesign teams on ECOs.
- Enable postâsilicon bringâup by generating test vectors, configuring scan/DFT hooks, and supporting FPGA/emulation platforms for firmware and software teams.
- Mentor junior engineers on verification methodology, code reviews, and best practices; champion continuousâintegration flows, regressions and results dashboards.
- Track industry advances in formal verification, emulation, coverageâdriven flows, RISCâV vectors, and AIâcentric design techniques to keep Flux at the forefront of silicon quality.
Skills & Experience
- 3+ years in digital ASIC/SoC design & verification, with at least two tapeâouts.
- Mastery of SystemVerilog/UVM, functional coverage, constraintârandom stimulus and scoreboards.
- Deep understanding of clockâdomain crossing, reset and powerâdomain management, DFT/scan and lowâpower (UPF/CPF) methodologies.
- Strong scripting (Python, Tcl, shell) to automate regressions and data analysis.
- Proven debug skills across RTL, gateâlevel and emulation environments.
Frequent travel is expected between our Austin and London offices.
Weâre building fast and that includes our benefits. More exciting additions are coming soon for the Flux crew.
If you are passionate about pushing the boundaries of what\’s possible in AI and thrive in a high-energy, fast-paced environment, we want to hear from you. Apply now to join Flux and be a key player in shaping the future of computing.
Seniority level
-
Seniority level
Mid-Senior level
Employment type
-
Employment type
Full-time
Job function
-
Job function
Engineering and Information Technology
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Industries
Semiconductor Manufacturing
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Digital Design Engineer - Verification employer: PageBolt WordPress
Contact Detail:
PageBolt WordPress Recruiting Team
StudySmarter Expert Advice đ¤Ť
We think this is how you could land Digital Design Engineer - Verification
â¨Tip Number 1
Familiarise yourself with the latest trends in digital design and verification, especially around SystemVerilog and UVM. This knowledge will not only help you during interviews but also demonstrate your passion for the field.
â¨Tip Number 2
Network with professionals in the semiconductor industry, particularly those working in ASIC design and verification. Attend relevant meetups or online forums to build connections that could lead to referrals at Flux Computing.
â¨Tip Number 3
Prepare to discuss specific projects where you've implemented verification strategies. Be ready to explain your role in ensuring first-silicon success and how you tackled challenges related to power, performance, and area trade-offs.
â¨Tip Number 4
Showcase your scripting skills in Python, Tcl, or shell by discussing how you've automated processes in previous roles. This will highlight your ability to improve efficiency and contribute to continuous integration flows at Flux.
We think you need these skills to ace Digital Design Engineer - Verification
Some tips for your application đŤĄ
Tailor Your CV: Make sure your CV highlights relevant experience in digital ASIC/SoC design and verification. Emphasise your mastery of SystemVerilog/UVM and any specific projects that demonstrate your skills in functional coverage and low-power methodologies.
Craft a Compelling Cover Letter: In your cover letter, express your passion for AI and semiconductor technology. Mention how your background aligns with the responsibilities outlined in the job description, particularly your experience with verification environments and collaboration with RTL designers.
Showcase Your Technical Skills: Include specific examples of your scripting abilities in Python, Tcl, or shell. Highlight any instances where you automated regressions or data analysis, as this is crucial for the role at Flux Computing.
Prepare for Potential Questions: Anticipate questions related to your experience with clock-domain crossing, reset management, and DFT/scan methodologies. Be ready to discuss how you've tackled complex verification challenges in past projects.
How to prepare for a job interview at PageBolt WordPress
â¨Showcase Your Technical Skills
Be prepared to discuss your experience with SystemVerilog and UVM in detail. Highlight specific projects where you implemented verification environments, and be ready to explain your approach to functional coverage and constraint-random stimulus.
â¨Demonstrate Problem-Solving Abilities
Expect to face technical questions that assess your debugging skills across RTL and gate-level environments. Prepare examples of corner-case bugs you've resolved and how you balanced power, performance, and area trade-offs during verification.
â¨Emphasise Collaboration Experience
Since the role involves working closely with RTL designers, share experiences where you collaborated on micro-architectures or resolved issues as a team. This will show your ability to work in a fast-paced, innovative environment.
â¨Stay Updated on Industry Trends
Research recent advances in formal verification and AI-centric design techniques. Being knowledgeable about current trends will demonstrate your passion for the field and your commitment to keeping Flux at the forefront of silicon quality.
