Senior FPGA Architect: Quantum Hardware & Real-Time DSP

The Mission At OQC, we aren’t just theorising about the future; we’re building it. Born from a philosophy of bold innovation, we’ve successfully transitioned quantum computing from an academic dream into a commercial reality. The most exciting thing is that we’re just getting started. As a Senior FPGA Engineer, you’ll play a critical role in designing and delivering the precision control hardware that powers our quantum computing systems. You’ll help solve complex technical challenges across FPGA architecture, high-speed data systems, and real-time signal processing — contributing directly to the advancement of scalable quantum computing technologies. The Role We’re looking for a Senior FPGA Engineer to join our Advanced Product Development Group (APD), working on purpose-built FPGA hardware for quantum computing applications. This role combines deep technical expertise with cross-functional collaboration, system-level thinking, and mentorship responsibilities within a highly innovative engineering environment. What You'll Be Working On Defining scalable FPGA architectures with a focus on deterministic timing, synchronization, maintainability, and multi-card communication. Designing, implementing, and verifying complex RTL for high-performance microwave and RF applications. Developing interfaces and control logic for high-speed ADCs, DACs, memory systems, and RF SoC platforms. Implementing real-time DSP algorithms optimized for FPGA resources and multi-clock domain designs. Supporting hardware bring-up, lab integration, verification activities, and system-level testing. Collaborating closely with Electronics, Embedded Software, Mechanical, Cryogenic, and Deployment teams to deliver fully integrated systems. Mentoring junior engineers through code reviews, technical guidance, and development best practices while contributing to project planning and technical documentation. What We're Looking For Commercial experience in FPGA design and verification within complex hardware environments. Experience with System Verilog, and/or VHDL. Expert-level proficiency in Verilog and deep understanding of FPGA architectures. Strong experience achieving timing closure on high-utilization FPGA designs and writing timing constraints. Experience developing systems involving high-speed ADCs/DACs, synchronization across multiple boards/subsystems, and real-time DSP. Ability to work independently on technically challenging projects while balancing delivery, quality, and risk. Experience collaborating across multidisciplinary engineering teams in fast-paced R