Datapath Formal Verification Engineer

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products powered by Apple Silicon. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product.

The Datapath Formal Verification team mathematically proves the correctness of Apple Silicon's arithmetic and datapath logic — from floating-point units to complex data transformation pipelines — eliminating entire classes of bugs before silicon is fabricated. We are looking for engineers who combine rigorous mathematical thinking with practical problem-solving. You will work at the boundary between architecture and micro‑architecture, formalising design intent and verifying design implementations. Full training is provided in hardware design, computer arithmetic, and formal verification tooling; what we need is the ability to construct and critically examine rigorous proofs, and the curiosity to push the boundaries of what formal methods can achieve at scale.

As a member of the Datapath Formal Verification team, you will collaborate with Apple Silicon's design engineers to develop formal micro‑architecture specifications for mathematically intensive components. Your work will span the full formal verification lifecycle: understanding architectural intent, formalising the refinement from architecture to micro‑architecture, building verification plans, writing and proving properties, debugging failures, and driving design changes when issues are found. You will develop reusable formal models and verification IP, and as you grow in the role there will be opportunities to explore areas such as correct‑by‑construction design methodologies and novel verification strategies for previously intractable micro‑architectures.

Responsibilities

• Develop formal specifications that capture the intended behaviour of datapath and arithmetic micro‑architectures
• Formalise the refinement relationship between architectural specifications and micro‑architectural implementations
• Create and execute comprehensive formal verification plans for datapath components
• Write, debug, and prove formal properties, applying abstraction and decomposition techniques as needed
• Identify design bugs; work with design teams to root‑cause issues and verify fixes
• Develop and maintain reusable formal models, reference models, and verification IP
• Evaluate and improve formal tool flows, including scripting, automation, and integration with broader verification infrastructure

Minimum Qualifications

• MS or PhD in Computer Science, Electrical Engineering, Mathematics, or a related discipline
• Comfortable with deep mathematical abstraction and able to construct, critically examine, and communicate rigorous proofs
• Tenacious and detail‑oriented — able to sustain focus through long proof efforts and identify subtle logical gaps in specifications and arguments
• Intellectually curious, with a genuine interest in understanding how mathematical systems work at a fundamental level
• Proficiency in at least one programming language (e.g., Python, C++) is strongly preferred

Preferred Qualifications

• Professional experience and/or PhD in formal methods, formal verification, computer arithmetic, or mathematical logic
• Experience with formal verification concepts such as model checking, theorem proving, or abstraction and refinement techniques
• Familiarity with EDA formal verification tools (e.g., JasperGold, VC Formal, or equivalent)
• Experience with assertion‑based verification using temporal logic languages (SVA, PSL)
• Domain knowledge or research interest in SAT/SMT solving, interactive theorem proving or Constrained Optimisation
• Familiarity with RTL design in SystemVerilog or VHDL
• Experience interpreting hardware architecture specifications and translating them into formal properties
• Experience with automation of engineering workflows, including the use of AI‑assisted tooling