Senior Digital Verification Engineer for AI ASIC

Senior Digital Verification Engineer for AI ASIC

Full-Time 63000 - 77000 Β£ / year (est.) No working from home possible
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At a Glance

  • Tasks: Lead the verification of cutting-edge AI ASICs and collaborate with diverse teams.
  • Company: Join OLIX, a leader in high-throughput data processing technology.
  • Benefits: Attractive salary, flexible work options, and opportunities for professional growth.
  • Other info: Dynamic team environment with a focus on innovation and career advancement.
  • Why this job: Make a significant impact in AI technology while mentoring the next generation of engineers.
  • Qualifications: Experience in digital verification and proficiency in SystemVerilog/UVM.

The predicted salary is between 63000 - 77000 Β£ per year.

OLIX is seeking Senior / Staff Digital Verification Engineers to own the verification of high-throughput, real-time data-processing silicon across GHz-class clock domains, from algorithm modelling to RTL sign-off and silicon bring-up.

You will collaborate with digital design, optics, and software teams, develop verification environments with SystemVerilog/UVM, constrained-random testing, and formal methods, and contribute to reusable verification methodologies while mentoring junior engineers.

Senior Digital Verification Engineer for AI ASIC employer: OLIX

At OLIX, we pride ourselves on being at the forefront of technological innovation, offering a dynamic work environment that fosters creativity and collaboration. As a Director of Quality, you will play a pivotal role in shaping our quality infrastructure, with ample opportunities for professional growth and development in a fast-paced industry. Our commitment to excellence is matched by our supportive culture, where every team member's contributions are valued, making OLIX an exceptional place to build a meaningful career.

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Contact Details:

OLIX Recruitment Team

We think you need these skills to ace Senior Digital Verification Engineer for AI ASIC

Digital Verification
SystemVerilog
UVM
Constrained-Random Testing
Formal Methods
Algorithm Modelling
RTL Sign-off