Architect, Staff & Senior Systems Software Engineer

About OLIX AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack‑scale co‑design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.

The Role We’re searching for Architect, Staff & Senior Systems Software Engineers to own how our next‑generation DX‑1 accelerator is brought to life as a production inference platform. DX‑1 is a dataflow architecture built specifically for decode, deployed in a disaggregated inference environment. Your mission is to make that hardware serve large AI models at rack scale by building and extending the runtime and serving stack that connects PyTorch and JAX down to the metal. This is a whole‑stack systems role. You’ll work where the runtime, the network, and the accelerator meet, partnering closely with hardware, compiler, and modelling teams to optimize serving performance. Your impact is measured not only by what you build but by the leverage you create: the standards you set, the systems and tooling other teams build on, and the direction you shape across the platform.

Responsibilities

• Own the Runtime & Serving Stack: Design, build, and extend the distributed inference and serving stack (e.g. vLLM, SGLang, NVIDIA Dynamo, TensorRT‑LLM) onto DX‑1, rather than treating any layer as a black box.
• Scale Distributed Inference: Define how inference scales across many accelerators: tensor / pipeline / data parallelism, collective communication patterns, KV‑cache management and offload, and memory‑aware scheduling across a disaggregated topology.
• Engineer for Reliability at Scale: Make distributed inference dependable across failure domains (fault handling, graceful degradation, load balancing, and recovery), and define the observability, tracing, and tooling standards that let teams diagnose problems across the runtime, network, and accelerator rather than through logs alone.
• Drive Bring‑Up: Evaluate system behaviour before silicon is fully available (simulation, emulation, FPGA prototyping, analytical modelling), root‑cause what breaks during bring‑up, and influence design decisions across hardware and software teams.
• Set Standards Across Teams: Identify the highest‑impact systems problems across teams and make sure they get solved; hold and articulate a clear technical bar and raise peers to it through review, pairing, and direct challenge; build leverage through systems, frameworks, and developing senior talent rather than solving everything personally.
• Shape Direction: Bring structure and clear direction to ambiguous, cross‑team problems, drive structural improvements with urgency, and shape strategic direction within the platform domain, informed by external research, competitive awareness, and industry connections that help generate talent and partnership pipelines.

Skills & Experience

• Deep experience in systems software, with hands‑on C/C++ and strong systems fundamentals across the runtime / network / accelerator boundary.
• Demonstrated ownership of a hard, end‑to‑end systems problem, ideally extending a distributed inference / serving stack (vLLM, SGLang, NVIDIA Dynamo, TensorRT‑LLM) in production, with specifics on what you built or changed and why.
• Distributed inference at scale: parallelism strategies, collective communication, KV‑cache and memory management, and reliability across distributed failure domains at cluster scale.
• Fluency at the framework boundary, connecting accelerators to PyTorch / JAX and serving stacks without treating either as opaque.
• Whole‑stack debugging: end‑to‑end and timeline tracing, workload replay, and reasoning from architectural constraints (SRAM, host–device latency, KV footprint, memory bandwidth, collective latency) to root cause.
• Strong, business‑aware judgment on speed / cost / quality trade‑offs, and a track record of structured, calm handling of late‑emerging risk.
• Excellent communication and the ability to align and influence cross‑functional teams (hardware, compiler, modelling) without relying on formal authority.
• Bachelor’s degree or higher in computer science, electrical engineering, mathematics, or a related field.

Nice to have

• Experience with dataflow or non‑GPU accelerator architectures; pre/post‑silicon bring‑up on custom hardware (ASIC/FPGA); production observability at scale (hardware counters, Prometheus/Grafana‑style export, device and cluster views).
• Adjacent depth is welcome: HPC cluster design, high‑speed networking, distributed systems, or heterogeneous compute platforms.

Compensation & Equity

• Competitive Salary: Commensurate with your experience, skills, and location.
• Equity & Ownership: Meaningful stock options. You’re not just joining the mission; you’re owning a piece of it.
• Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living‑Local Bonus if your residence is within 20 minutes of the office.
• Retirement Benefits: Employer‑contributed retirement plans to help you build long‑term financial security.

Due to U.S. export control regulations, candidates’ eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.