Senior Design Verification Engineer

Senior Design Verification Engineer

United Kingdom

B2B Contract

Profile

• Proven experience in testbench design and development using UVM methodology for IP/Subsystem/SoCs.

• Proven experience in verification sign-off at IP/Sub System/SoC level with test plan development, functional & code coverage analysis

• Proven experience in EDA tools from Cadence (Xcelium, Simvision, Verisium, vManager, Jasper) and / or Synopsys (VCS, Verdi)

• Understanding of software development for embedded CPUs, and experience in developing and debugging software.

• Basic experience in execution of Gate Level Netlist simulation with back-annotated timing.

• Basic experience on writing System Verilog assertions

• Basic understanding of Formal flow /methodologies

• Ability to question and identify weaknesses in specifications, tool environments, etc.

• Pro-active attituded engineer with proven experience in digital IP & SoC verification & good communication skills

• Fluency in English language.