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- Tasks: Lead the verification of digital and Analog Mixed-Signal designs, ensuring compliance and resolving issues.
- Company: Join a top semiconductor IC design company specialising in innovative digital power devices.
- Benefits: Enjoy a full-time role with opportunities for growth and collaboration in a dynamic environment.
- Why this job: Be part of a cutting-edge team, shaping technology that impacts everyday life while enhancing your skills.
- Qualifications: Experience with UVM, Cadence Virtuoso, Verilog AMS, and scripting languages like TCL and bash required.
- Other info: This is a mid-senior level position located in Cambridge, England.
The predicted salary is between 36000 - 60000 £ per year.
The engineer will work closely with the design team and be responsible for all aspects of verifying that the digital core is fully functionally compliant with the specification at the top level. They will manage the verification environment and develop models for analog.
Primary Job Responsibilities
- Managing the digital verification environment for the design
- Setting methodologies and guidelines for digital verification on the project
- Reviewing the internal/customer specification and generating a full test plan and environment to confirm compliance
- Reviewing RTL to debug and understand any issues, and propose solutions
- Working closely with the design team to resolve any issues
- Design of some digital sub-blocks
Qualifications
- BSEE +5 years or MSEE +3 years of relevant experience. At least 3 years of digital verification, including test writing and verification of several products
- Experience with using the Cadence Virtuoso software and AMS simulation environment
- Comfortable with exploring the analog schematic hierarchy in Cadence
- Able to write and debug System Verilog models. Previous real number modelling experience a plus
- Can create thorough block and system level SV assertions
- Experience in debugging simulation issues and bug identification
- A good understanding of UVM, and the ability to import an environment from an existing project and improve upon it
- Strong scripting skills is a highly desirable (csh, Python and TCL)
- Able to work well in a remote team environment, including good communication and inter-personal skills
- Self-starter able to manage his/her own time effectively
Seniority Level
- Mid-Senior level
Employment Type
- Full-time
Job Function
- Engineering and Information Technology
- Staffing and Recruiting
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Design Verification Engineer employer: MRL Consulting Group | Global Niche Technology Recruitment
Contact Detail:
MRL Consulting Group | Global Niche Technology Recruitment Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Design Verification Engineer
✨Tip Number 1
Familiarise yourself with Universal Verification Methodology (UVM) and ensure you can discuss its application in your previous projects. Being able to articulate how you've implemented UVM in your work will show your expertise and make you stand out.
✨Tip Number 2
Brush up on your skills with Cadence Virtuoso and Verilog AMS simulation. Consider doing a quick project or two to demonstrate your proficiency, as practical examples can really impress during discussions.
✨Tip Number 3
Network with professionals in the semiconductor industry, especially those who are already working in design verification roles. Engaging in conversations can provide insights into the company culture and expectations, which can be beneficial during interviews.
✨Tip Number 4
Prepare to discuss your experience with debugging RTL and resolving issues. Be ready to share specific examples of challenges you've faced and how you approached them, as this will showcase your problem-solving skills.
We think you need these skills to ace Design Verification Engineer
Some tips for your application 🫡
Understand the Role: Before applying, make sure you fully understand the responsibilities and requirements of a Design Verification Engineer. Familiarise yourself with Universal Verification Methodology (UVM), Cadence Virtuoso software, and Verilog AMS simulation.
Tailor Your CV: Highlight your relevant experience in digital and Analog Mixed-Signal (AMS) verification. Include specific projects where you've managed verification environments or developed test plans, showcasing your skills in RTL debugging and scripting.
Craft a Strong Cover Letter: Write a cover letter that connects your background to the job description. Emphasise your expertise in UVM-based verification and any experience with formal verification processes. Make it clear why you're a great fit for the role.
Proofread Your Application: Before submitting, carefully proofread your CV and cover letter. Check for any spelling or grammatical errors, and ensure that all technical terms are used correctly. A polished application reflects your attention to detail.
How to prepare for a job interview at MRL Consulting Group | Global Niche Technology Recruitment
✨Understand the Technical Requirements
Make sure you have a solid grasp of the technical skills required for the role, such as UVM, Verilog AMS modelling, and Cadence Virtuoso. Brush up on these topics and be prepared to discuss your experience with them in detail.
✨Prepare for Scenario-Based Questions
Expect questions that assess your problem-solving abilities in real-world scenarios. Think about past projects where you managed verification environments or resolved RTL/Gate simulation bugs, and be ready to explain your thought process.
✨Showcase Your Methodology Knowledge
Since the role involves setting methodologies and guidelines for verification, be prepared to discuss your approach to creating test plans and coverage plans. Highlight any frameworks or strategies you've successfully implemented in previous roles.
✨Communicate Effectively with Design Teams
Collaboration is key in this role. Be ready to share examples of how you've worked closely with design teams in the past to resolve issues. Emphasise your communication skills and ability to work as part of a team.
