We are seeking a senior ASIC design engineer to lead and deliver complex digital design for next-generation AI accelerators and high-performance SoC subsystems. The role spans architecture and microarchitecture through RTL implementation, verification, tape-out and silicon validation, with a strong focus on performance, power and area (PPA).
Key Responsibilities
- Define architecture and microarchitecture for AI accelerators and complex SoC blocks, including compute pipelines, memory hierarchies, interconnects and DMA.
- Develop synthesizable RTL using Verilog/SystemVerilog; optimize datapaths, control logic, pipelining and resource sharing.
- Design or integrate high-bandwidth memory and I/O subsystems, including LPDDR and PCIe; consider NoC, cache coherency and data movement.
- Drive design quality across simulation, lint, CDC/RDC, synthesis, timing analysis and collaboration with verification and physical-design teams.
- Support the ASIC lifecycle from specification and RTL through tape-out, silicon bring-up, post-silicon debug and production validation.
- Work with firmware, software and system teams on hardware/software interfaces and system-level integration.
Required Experience
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science or a related discipline.
- 10+ years of hands-on digital ASIC/SoC microarchitecture and RTL design experience.
- Strong Verilog/SystemVerilog skills and experience designing GPUs, NPUs, AI accelerators or complex SoC subsystems.
- Experience taking ASIC/SoC designs from specification through tape-out and silicon production.
- Knowledge of digital datapaths, memory subsystems, interconnects, clock/reset design and ASIC design flows.
- Working knowledge of PCIe and LPDDR technologies, plus experience with hardware/software integration or functional verification.
Preferred
- GPU/NPU or AI inference accelerator design; transformer, tensor or matrix-multiplication workloads.
- PCIe Gen5/Gen6, LPDDR5/5X/6, chiplets, die-to-die links, NoC, cache coherency or AMBA AXI/ACE/CHI.
- UVM/formal verification, FPGA prototyping or emulation; advanced process nodes and low-power design
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