At a Glance
- Tasks: Join our Verification Team to ensure high-quality silicon delivery through functional verification and debugging.
- Company: A leading tech company based in Cambridge and Bristol, focused on innovative silicon solutions.
- Benefits: Enjoy a competitive rate, hybrid working options, and the chance to work with cutting-edge technology.
- Why this job: Be part of a dynamic team that values collaboration and innovation in hardware systems.
- Qualifications: Experience in silicon/ASIC/CPU verification and proficiency in SystemVerilog, Python, and C++ required.
- Other info: This is a 12-month contract role with opportunities for professional growth.
The predicted salary is between 48000 - 72000 £ per year.
A client of mine based in Cambridge and Bristol is looking for several Verification Engineers to join our client's Verification Team on a 12-month contract. This role is critical in supporting verification efforts to ensure high-quality silicon delivery that meets architectural and design specifications.
The successful candidate will be involved in functional verification, coverage closure, and diagnostic activities across complex hardware systems.
The Team: The Verification Team operates within the Design Group and collaborates closely with both the Logical and Physical Design Teams. The team's mission is to ensure that RTL implementations align fully with architectural specifications for products.
Key Responsibilities:
- Execute verification tasks within the silicon design lifecycle
- Develop and manage verification plans and functional coverage specifications
- Provide feedback to architects and design engineers
- Develop tests and perform failure triage/debug
- Contribute to the shared verification infrastructure and methodology
- Facilitate cross-site communication and collaboration
Skills and Experience:
- Industry experience in silicon/ASIC/CPU verification
- Strong understanding of verification methodologies and planning
- Proven ability to lead, plan, and execute verification tasks independently
- Skilled in debugging complex issues across software/hardware boundaries
- Proficient in: SystemVerilog, Python, C++, Linux environments
Desirable Skills:
- UVM (Universal Verification Methodology)
- SVA (SystemVerilog Assertions)
- Assembly language familiarity
- Experience with toolchains such as LLVM or GCC
- DVCS tools (e.g., Git)
- Experience with job schedulers (SGE or similar DRMS)
- XML/XPath/XSLT
- Web technologies: HTML/DOM, JavaScript, SQL
Working Pattern: Hybrid working: 3 days onsite in Cambridge or Bristol, 2 days remote.
Verification Engineer employer: Microtech Global Ltd
Contact Detail:
Microtech Global Ltd Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Verification Engineer
✨Tip Number 1
Familiarise yourself with the specific verification methodologies mentioned in the job description, such as UVM and SVA. Having a solid understanding of these will not only boost your confidence but also demonstrate your commitment to the role during discussions.
✨Tip Number 2
Network with current or former employees of the company on platforms like LinkedIn. Engaging in conversations about their experiences can provide you with valuable insights into the team dynamics and expectations, which you can leverage in your interactions.
✨Tip Number 3
Brush up on your debugging skills, especially in complex software/hardware environments. Being able to discuss specific examples of how you've tackled similar challenges in the past can set you apart from other candidates.
✨Tip Number 4
Prepare to discuss your experience with tools like Git and job schedulers. Highlighting your familiarity with these tools during interviews can show that you're ready to hit the ground running and contribute to the team's workflow.
We think you need these skills to ace Verification Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights relevant experience in silicon/ASIC/CPU verification. Emphasise your understanding of verification methodologies and any leadership roles you've held in previous projects.
Craft a Strong Cover Letter: In your cover letter, explain why you're interested in the Verification Engineer role specifically. Mention your experience with SystemVerilog, Python, and C++, and how these skills will contribute to the team's success.
Showcase Relevant Projects: If you have worked on projects involving functional verification or debugging complex issues, include these in your application. Detail your contributions and the outcomes to demonstrate your capabilities.
Highlight Soft Skills: Since the role involves collaboration with various teams, mention your communication skills and ability to work in a hybrid environment. Provide examples of how you've successfully collaborated across different teams or locations.
How to prepare for a job interview at Microtech Global Ltd
✨Understand the Role
Make sure you thoroughly understand the responsibilities of a Verification Engineer. Familiarise yourself with functional verification, coverage closure, and diagnostic activities, as these will likely be key discussion points during your interview.
✨Showcase Your Technical Skills
Be prepared to discuss your experience with SystemVerilog, Python, and C++. Highlight any projects where you've successfully debugged complex issues across software and hardware boundaries, as this is crucial for the role.
✨Prepare for Methodology Questions
Since the role requires a strong understanding of verification methodologies, brush up on UVM and SVA. Be ready to explain how you've applied these methodologies in past projects and how they can benefit the team.
✨Demonstrate Collaboration Skills
The Verification Team collaborates closely with other teams, so be prepared to discuss your experience in cross-site communication and teamwork. Share examples of how you've facilitated collaboration in previous roles.