Project Engineer Engineering

Project Engineer Engineering

Full-Time 36000 - 60000 £ / year (est.) No home office possible
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At a Glance

  • Tasks: Lead verification of open-source digital designs and develop innovative testbenches.
  • Company: Exciting tech company in Cambridge with a focus on cutting-edge engineering.
  • Benefits: Competitive salary, flexible working hours, and opportunities for mentorship.
  • Why this job: Join a team that shapes the future of technology and drives innovation.
  • Qualifications: Experience in SystemVerilog/UVM and a passion for mentoring others.
  • Other info: Dynamic work environment with great potential for career advancement.

The predicted salary is between 36000 - 60000 £ per year.

We have an exciting opportunity in Cambridge for a Principal Verification Engineer to lead verification of open-source digital designs, including OpenTitan, RISC-V cores, OTBN, crypto accelerators, and peripherals.

What You'll Do:

  • Lead design, implementation, and debugging of SystemVerilog/UVM testbenches
  • Develop verification plans, tests, and coverage strategies
  • Mentor engineers and drive best practices

Project Engineer Engineering employer: Microtech Global Ltd

Join a forward-thinking company in Cambridge that values innovation and collaboration, offering a dynamic work culture where your contributions directly impact cutting-edge open-source digital designs. With a strong emphasis on employee growth, you will have access to mentorship opportunities and professional development, ensuring you thrive in your role as a Principal Verification Engineer. Enjoy the unique advantage of working in a vibrant tech hub, surrounded by like-minded professionals passionate about pushing the boundaries of technology.
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Contact Detail:

Microtech Global Ltd Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land Project Engineer Engineering

✨Tip Number 1

Network like a pro! Reach out to folks in the industry, attend meetups, and connect with people on LinkedIn. You never know who might have the inside scoop on job openings or can refer you directly.

✨Tip Number 2

Prepare for those interviews! Research common questions for Project Engineers and practice your answers. We recommend doing mock interviews with friends or using online platforms to get comfortable.

✨Tip Number 3

Showcase your skills! Create a portfolio of your projects, especially those involving SystemVerilog/UVM testbenches. This will give potential employers a clear view of what you can bring to the table.

✨Tip Number 4

Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, we love seeing candidates who are proactive about their job search!

We think you need these skills to ace Project Engineer Engineering

SystemVerilog
UVM
Verification Planning
Testbench Development
Debugging Skills
Mentoring
Coverage Strategies
Open-source Digital Design Knowledge
RISC-V Architecture Understanding
Crypto Accelerators Knowledge
Peripherals Design Experience
Best Practices Implementation

Some tips for your application 🫡

Tailor Your CV: Make sure your CV highlights relevant experience and skills that match the job description. We want to see how your background aligns with leading verification of digital designs, so don’t hold back on showcasing your SystemVerilog/UVM expertise!

Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re excited about the role and how you can contribute to our team. Mention specific projects or experiences that relate to the verification of open-source designs.

Showcase Your Problem-Solving Skills: In your application, highlight instances where you've successfully tackled complex engineering challenges. We love seeing how you approach debugging and implementation, especially in relation to verification plans and testbenches.

Apply Through Our Website: We encourage you to apply directly through our website for a smoother process. It helps us keep track of your application and ensures you don’t miss out on any important updates from us!

How to prepare for a job interview at Microtech Global Ltd

✨Know Your Tech Inside Out

Make sure you’re well-versed in SystemVerilog and UVM. Brush up on your knowledge of open-source digital designs, especially OpenTitan and RISC-V cores. Being able to discuss specific projects or challenges you've faced with these technologies will show your expertise.

✨Prepare Your Verification Plans

Before the interview, think about how you would develop verification plans and coverage strategies. Be ready to share examples of how you've implemented these in past roles. This will demonstrate your ability to lead and mentor others in best practices.

✨Showcase Your Problem-Solving Skills

Expect to be asked about debugging and implementation challenges. Prepare a couple of scenarios where you successfully resolved issues in testbenches. Highlight your thought process and the steps you took to arrive at a solution.

✨Ask Insightful Questions

Interviews are a two-way street! Prepare thoughtful questions about the team’s current projects, their approach to mentoring, and how they measure success in verification. This shows your genuine interest in the role and helps you assess if it’s the right fit for you.

Project Engineer Engineering
Microtech Global Ltd
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