Principal Verification Engineer
Principal Verification Engineer

Principal Verification Engineer

Full-Time 54000 - 84000 £ / year (est.) No home office possible
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At a Glance

  • Tasks: Lead verification of cutting-edge digital designs and mentor fellow engineers.
  • Company: Innovative tech firm in Cambridge focused on open-source projects.
  • Benefits: Competitive salary, flexible working options, and opportunities for professional growth.
  • Why this job: Join a pioneering team and shape the future of digital design technology.
  • Qualifications: Experience in SystemVerilog/UVM and strong leadership skills.
  • Other info: Dynamic work environment with a focus on innovation and collaboration.

The predicted salary is between 54000 - 84000 £ per year.

We have an exciting opportunity in Cambridge for a Principal Verification Engineer to lead verification of open-source digital designs, including OpenTitan, RISC-V cores, OTBN, crypto accelerators, and peripherals.

What You’ll Do:

  • Lead design, implementation, and debugging of SystemVerilog/UVM testbenches
  • Develop verification plans, tests, and coverage strategies
  • Mentor engineers and drive best practices

Principal Verification Engineer employer: Microtech Global Ltd

Join a forward-thinking company in Cambridge that values innovation and collaboration, offering a dynamic work culture where your contributions as a Principal Verification Engineer will directly impact cutting-edge open-source digital designs. With a strong emphasis on employee growth, you will have access to mentorship opportunities and professional development, all while enjoying the vibrant tech community of Cambridge, known for its rich history and thriving ecosystem.
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Contact Detail:

Microtech Global Ltd Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land Principal Verification Engineer

✨Tip Number 1

Network like a pro! Reach out to folks in the industry, especially those who work with open-source digital designs. A friendly chat can lead to insider info about job openings or even a referral.

✨Tip Number 2

Show off your skills! Create a portfolio showcasing your work with SystemVerilog and UVM testbenches. This will give potential employers a taste of what you can do and set you apart from the crowd.

✨Tip Number 3

Prepare for interviews by brushing up on your technical knowledge and soft skills. Be ready to discuss your experience with verification plans and mentoring, as these are key aspects of the Principal Verification Engineer role.

✨Tip Number 4

Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, we love seeing candidates who take that extra step to connect with us directly.

We think you need these skills to ace Principal Verification Engineer

SystemVerilog
UVM
Verification Planning
Testbench Development
Debugging Skills
Mentoring
Best Practices Implementation
Open-Source Digital Design Knowledge
RISC-V Architecture Understanding
Crypto Accelerators Knowledge
Peripherals Verification
Coverage Strategies Development

Some tips for your application 🫡

Tailor Your CV: Make sure your CV is tailored to the Principal Verification Engineer role. Highlight your experience with SystemVerilog and UVM, and don’t forget to mention any relevant projects or achievements that align with our needs.

Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re passionate about verification engineering and how your skills can contribute to our exciting projects like OpenTitan and RISC-V cores.

Showcase Your Mentoring Skills: Since mentoring is key in this role, share examples of how you've guided others in your previous positions. We love seeing how you’ve helped teams grow and adopt best practices!

Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for this fantastic opportunity in Cambridge!

How to prepare for a job interview at Microtech Global Ltd

✨Know Your Tech Inside Out

As a Principal Verification Engineer, you'll need to be well-versed in SystemVerilog and UVM. Brush up on your knowledge of these technologies and be ready to discuss your past experiences with them. Prepare to explain how you've implemented testbenches and tackled debugging challenges.

✨Showcase Your Leadership Skills

This role involves mentoring engineers and leading verification efforts. Be prepared to share examples of how you've successfully led teams or projects in the past. Highlight your ability to drive best practices and foster collaboration among team members.

✨Prepare for Technical Questions

Expect technical questions that assess your understanding of verification plans, tests, and coverage strategies. Practice articulating your thought process when developing these elements. It’s also a good idea to review common pitfalls in verification and how to avoid them.

✨Demonstrate Your Passion for Open Source

Since this position involves working with open-source digital designs like OpenTitan and RISC-V cores, show your enthusiasm for open-source projects. Discuss any relevant contributions you've made or how you stay updated with the latest developments in the open-source community.

Principal Verification Engineer
Microtech Global Ltd

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