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- Tasks: Apply formal verification techniques to ensure the correctness of complex digital designs.
- Company: Join a dynamic team at a cutting-edge Google HPC programme.
- Benefits: Negotiable salary, remote work, and opportunities for professional growth.
- Why this job: Make a real impact on innovative chiplet-based designs while working remotely.
- Qualifications: BSc/MSc in relevant fields and strong knowledge of SystemVerilog.
- Other info: Collaborative environment with opportunities to develop your skills.
The predicted salary is between 36000 - 60000 £ per year.
Are you passionate about applying formal verification techniques to ensure the functional correctness of complex digital ASIC designs? We have an exciting opportunity for a Formal Verification Engineer to join a dynamic team, working remotely with occasional visits to the London office.
You will apply formal verification techniques to ensure the correctness and completeness of chiplet-based designs featuring multi-processors and high-speed I/Os, working closely with RTL and DV teams.
Key Responsibilities- Develop and optimize SystemVerilog Assertions (SVA) and formal properties
- Perform formal verification at block, subsystem, and full-chip levels
- Create abstractions, assumptions, and constraints for proofs
- Identify bugs, dead code, unreachable coverage, and vacuous proofs
- Debug counterexamples and proof failures using JasperGold, VC Formal, and Questa Formal
- Collaborate with RTL and DV teams to achieve verification coverage closure
- BSc or MSc in EE, CE, CS, Mathematics, or Physics
- Strong knowledge of SystemVerilog/Verilog and digital design
- Hands-on experience with formal verification methodologies
- Proficiency with SVA (PSL a plus)
- Experience with at least one formal tool (JasperGold, VC Formal, or Questa Formal)
- Strong debugging and problem-solving skills
- Semiconductor HPC or complex SoC designs
- AXI, CPU, DSP, DDR, PCIe, or HBM verification
- Familiarity with UVM and simulation-based flows
- Scripting experience (Python, TCL, Perl)
- Strong analytical mindset and attention to detail
- Clear technical communication skills
- Proactive, collaborative, and self-driven
If interested, please send your CV to tee@microtech-global.com and let's have a conversation.
Formal Verification Engineer employer: Microtech Global Ltd
Contact Detail:
Microtech Global Ltd Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Formal Verification Engineer
✨Tip Number 1
Network like a pro! Reach out to folks in the industry, especially those who work with formal verification. LinkedIn is your best mate here – connect, engage, and don’t be shy to ask for a chat about their experiences.
✨Tip Number 2
Show off your skills! If you’ve got any projects or contributions related to SystemVerilog or formal verification, make sure to highlight them in conversations. Real-world examples can really set you apart from the crowd.
✨Tip Number 3
Prepare for technical interviews by brushing up on your debugging and problem-solving skills. Practice explaining your thought process clearly, as communication is key when collaborating with RTL and DV teams.
✨Tip Number 4
Don’t forget to apply through our website! It’s a great way to ensure your application gets noticed. Plus, we love seeing candidates who take that extra step to engage with us directly.
We think you need these skills to ace Formal Verification Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your experience with formal verification techniques and digital design. We want to see how your skills align with the role, so don’t be shy about showcasing relevant projects or tools you've used!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to express your passion for formal verification and how you can contribute to our dynamic team. Keep it concise but impactful – we love a good story!
Showcase Your Technical Skills: Be specific about your technical expertise in SystemVerilog, SVA, and any formal tools you've worked with. We’re looking for those hands-on experiences that demonstrate your problem-solving skills and attention to detail.
Apply Through Our Website: We encourage you to apply through our website for a smoother process. It helps us keep track of applications better and ensures you don’t miss out on any important updates from us!
How to prepare for a job interview at Microtech Global Ltd
✨Know Your Formal Verification Inside Out
Make sure you brush up on formal verification techniques and tools like JasperGold, VC Formal, and Questa Formal. Be ready to discuss your hands-on experience with these tools and how you've applied them in past projects.
✨Showcase Your SystemVerilog Skills
Since the role requires strong knowledge of SystemVerilog and SVA, prepare to demonstrate your understanding. You might be asked to write or analyse assertions, so practice explaining your thought process clearly.
✨Prepare for Technical Questions
Expect questions that dive deep into digital design concepts and debugging strategies. Brush up on topics like multi-processors, high-speed I/Os, and common bugs in chiplet-based designs to show your expertise.
✨Highlight Your Collaboration Skills
This role involves working closely with RTL and DV teams, so be ready to discuss examples of how you've successfully collaborated in the past. Emphasise your proactive approach and ability to communicate technical details effectively.