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- Tasks: Drive innovation in semiconductor projects through design verification and testing.
- Company: Cutting-edge tech team based in Cambridge, UK.
- Benefits: Generous leave, private medical insurance, and opportunities for training.
- Why this job: Join a dynamic team and work on next-gen technology that shapes the future.
- Qualifications: 5+ years in design verification with strong SystemVerilog and UVM skills.
- Other info: Collaborative environment with chances to attend industry conferences.
The predicted salary is between 48000 - 84000 £ per year.
An exciting opportunity has just opened for a Senior Design Verification Engineer to join a cutting-edge team in Cambridge, UK, driving innovation in next‑gen semiconductor projects.
Location: Cambridge, UK
Duration: Permanent
Salary: Negotiable (depending on qualifications and experience)
Position Overview: As a Senior Design Verification Engineer, you will apply industrial‑strength verification to both system‑ and block‑level designs, including RISC‑V cores, OTBN (cryptographic CPU), AES accelerators, and peripherals like USB, I2C, and SPI.
Key Responsibilities:
- Design, implement, and debug block/system‑level tests and testbenches using SystemVerilog and UVM
- Develop test and coverage plans for new and updated designs
- Triage and debug nightly regressions
- Review contributions to open‑source projects
- Enhance test and CI infrastructure
- Collaborate on academic/industry publications
- Stay current with verification best practices and introduce improvements
Candidate Requirements:
Essential:
- 5+ years industry experience in design verification
- Strong SystemVerilog and UVM expertise
- Experience across the full verification cycle (planning to tape‑out)
- Able to provide estimates and coordinate with project managers
- Comfortable in multidisciplinary, multi‑organisation teams
- Familiar with Git and code review tools (GitHub, GitLab, Gerrit)
- Programming in C and/or Python for tests and automation
- Undergraduate degree in a technical discipline or equivalent
Desirable:
- Experience with multiple hardware block types
- Knowledge of security countermeasures (fault injection, side‑channel attacks)
- Experience with RISC‑V ISA or other instruction sets
- Familiarity with formal verification tools (e.g., JasperGold)
Benefits:
- 25 days annual leave + 8 bank holidays
- Employer pension contribution
- Private medical insurance, income protection, critical illness and life cover
- Opportunities to attend industry conferences and training
If you could be interested in this position, please get in touch and share your CV with me at tee@microtech-global.com.
Senior Design Verification Engineer employer: microTECH Global Limited
Contact Detail:
microTECH Global Limited Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Senior Design Verification Engineer
✨Tip Number 1
Network like a pro! Reach out to your connections in the semiconductor industry, especially those who might know about opportunities at companies you're interested in. A personal recommendation can make all the difference.
✨Tip Number 2
Show off your skills! Create a portfolio or GitHub repository showcasing your projects and contributions, especially those related to SystemVerilog and UVM. This gives potential employers a tangible look at what you can do.
✨Tip Number 3
Prepare for interviews by brushing up on common design verification scenarios. Be ready to discuss your experience with RISC-V cores and other relevant technologies. Practice makes perfect, so consider mock interviews with friends or mentors.
✨Tip Number 4
Don't forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, we love seeing candidates who take that extra step to connect with us directly.
We think you need these skills to ace Senior Design Verification Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your experience in design verification, especially with SystemVerilog and UVM. We want to see how your skills align with the role, so don’t be shy about showcasing relevant projects!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re excited about this Senior Design Verification Engineer position and how your background makes you a perfect fit for our cutting-edge team.
Showcase Your Collaboration Skills: Since we work in multidisciplinary teams, it’s important to highlight your ability to collaborate effectively. Share examples of how you’ve worked with others in past projects, especially in a multi-organisation setting.
Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you don’t miss out on any important updates regarding your application status!
How to prepare for a job interview at microTECH Global Limited
✨Know Your Stuff
Make sure you brush up on your SystemVerilog and UVM knowledge. Be ready to discuss specific projects where you've applied these skills, especially in relation to block/system-level designs. This will show that you’re not just familiar with the tools but can also use them effectively.
✨Showcase Your Experience
Prepare to talk about your experience across the full verification cycle. Highlight any challenges you faced and how you overcame them. This is your chance to demonstrate your problem-solving skills and your ability to coordinate with project managers.
✨Collaboration is Key
Since this role involves working in multidisciplinary teams, be ready to share examples of how you've successfully collaborated with others. Discuss any open-source contributions or publications you've been part of, as this shows your commitment to the field and teamwork.
✨Stay Current
Familiarise yourself with the latest verification best practices and tools. Mention any recent trends or technologies you've explored, especially those related to security countermeasures or formal verification tools. This will demonstrate your proactive approach to professional development.