Design Verification Manager – Lead Multi‑Site DV Teams in Cambridge

A leading semiconductor organization is seeking a Design Verification Manager to lead a multi-site team in Cambridge. This role involves managing the verification of complex IC projects and driving methodology adoption. The ideal candidate will have strong expertise in silicon design verification, UVM, and SystemVerilog, along with experience managing remote teams. The position offers competitive salary and substantial benefits, including 25 days of annual leave and a private medical insurance plan. #J-18808-Ljbffr