Principal Engineer- Design Implementation in Cambridge

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

As part of the Microcontroller (MCU) SoC Design group, the successful candidate will be responsible for Design Implementation (Synthesis/STA/Timing closure) of 32-bit microcontrollers. The role will include driving and optimizing synthesis, power optimization, static timing analysis, and logic verification using an industry-leading SoC design flow. It will require a proactive candidate with a proven record of success in delivering leading edge SoC designs. The candidate is required to drive and enhance Synthesis, Static Timing, and Power Optimization methodologies for the MCU silicon design group.

Duties and responsibilities include:

• Develop timing constraints, drive SoC timing budgets, power optimization, formal verification, timing closure and other sign-off activities.
• Drive low power implementation and optimization methodologies using UPF/CPF.
• Work closely with digital, analog, and physical design teams to optimize for performance, power, and area.

Requirements/Qualifications:

• Bachelor’s degree in electrical engineering with at least 10+ years of experience in ASIC implementation activities such as synthesis and STA.
• Extensive experience in RTL2Netlist implementation flows.
• Strong knowledge in Cadence & Synopsys tools for synthesis, static timing analysis and other activities.
• Strong scripting skills in TCL, Perl and other programming languages.
• Very good interpersonal skills and able to interact well with other members in the functional teams of the business unit.
• Good communication skills.

Travel Time: 0% - 25%