MediaTek Incorporated is a global fabless semiconductor company that enables nearly 2 billion connected devices a year. We are a market leader in developing innovative systems-on-chip (SoC) for mobile devices, home entertainment, connectivity and IoT products. MediaTek is the number one Wi‑Fi supplier across broadband, retail routers, consumer electronics devices and gaming, and its Wi‑Fi 6 chipsets are powering the latest networking equipment for faster computing experience's.
With market leader position of MediaTek SoC design, MediaTek GPU IP team is committed for industry leading, feature rich and PPA competitive GFX IP optimization, customization and development. The GFX IP will be not only deployed in flagship and mainstream mobile SoC, but also served as fundamental technology for adjacent markets like laptop, IoT, AI, VR/AR, automotive etc. The team is now hiring all areas of GPU talents in all levels including Architecture, Architecture, SW driver, Compiler, Performance, Power and Model engineers to join Cambourne, Cambridge.
Role and Responsibilities
- Define and develop best‑in‑class GPU architecture and performance/power models for next‑generation MediaTek SoCs.
- Build and maintain cycle‑accurate / performance / functional models of GPU subsystems (e.g., shader cores, fixed‑function units, memory hierarchy, interconnect).
- Use modeling and profiling to explore architectural trade‑offs (performance, power, area) and guide micro‑architecture decisions.
- Analyze workloads (games, graphics benchmarks, GPU compute, AI/ML kernels) using simulation and hardware profiling to identify bottlenecks and optimization opportunities.
- Collaborate closely with model, RTL, DV, driver and compiler and performance teams to ensure architectural intent is correctly implemented, verified and tuned.
- Provide architectural input to compiler/driver/runtime teams to maximize utilization of GPU hardware through software optimizations.
- Develop methodologies, tools and automation flows for GPU performance estimation, capacity planning and regression analysis.
- Lead the debug and root‑cause analysis of performance, power and bandwidth issues observed in models, emulation and silicon.
- Drive cross‑team technical discussions, present modeling results and architectural proposals, and influence roadmap decisions for next‑generation GPUs.
Requirements
- MS or higher in Computer Science, Electrical/Computer Engineering or a closely related field.
- Hands on Experience in GPU, graphics, high‑performance compute, AI accelerator, or related architecture/modeling areas.
- Strong experience with performance and/or cycle‑accurate modeling, simulation frameworks, or architectural exploration for complex SoCs or accelerators.
- Solid understanding of graphics and compute APIs such as Vulkan, OpenGL, DirectX and/or GPU compute frameworks (e.g., OpenCL, CUDA, Metal).
Preferred Qualifications (Nice to Have)
- Experience with mobile/low‑power GPU design and power/performance trade‑off analysis.
- Background in compiler, driver, or runtime optimization for GPUs or accelerators.
- Familiarity with ML/AI workloads, DNN operators and their mapping onto GPU or accelerator architectures.
- Experience collaborating with silicon implementation, physical design and DV teams on performance and power sign‑off.
