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- Tasks: Design and implement verification tests for exciting open-source projects.
- Company: Join lowRISC, a pioneering tech company based in Cambridge.
- Benefits: Enjoy a competitive salary, 25 days annual leave, and private medical insurance.
- Other info: Hybrid working options available after probation for better work-life balance.
- Why this job: Make a real impact in the open-source community while working with cutting-edge technology.
- Qualifications: 5+ years in design verification, expertise in SystemVerilog and UVM required.
The predicted salary is between 68000 - 88000 £ per year.
lowRISC in Cambridge is looking for a Senior DV Engineer to design and implement verification tests for open-source projects. The role requires over 5 years of experience in design verification, significant expertise in SystemVerilog and UVM, and a degree in a technical discipline.
Competitive salary ranges from £68,000 to £88,000, with benefits including:
- 25 days annual leave
- A generous pension contribution
- Private medical insurance
Hybrid working options available after probation.
Senior Open-Source DV Engineer – Hybrid in Cambridge employer: lowRISC
Contact Detail:
lowRISC Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Senior Open-Source DV Engineer – Hybrid in Cambridge
✨Tip Number 1
Network like a pro! Reach out to folks in the industry, especially those at lowRISC or similar companies. A friendly chat can sometimes lead to opportunities that aren’t even advertised.
✨Tip Number 2
Show off your skills! If you’ve got a portfolio of projects or contributions to open-source, make sure to highlight them. It’s a great way to demonstrate your expertise in SystemVerilog and UVM.
✨Tip Number 3
Prepare for the interview by brushing up on common DV scenarios and challenges. We recommend practising with mock interviews to get comfortable discussing your experience and problem-solving approach.
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, we love seeing candidates who are proactive about their job search.
We think you need these skills to ace Senior Open-Source DV Engineer – Hybrid in Cambridge
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your experience in design verification and your expertise in SystemVerilog and UVM. We want to see how your skills align with the role, so don’t be shy about showcasing relevant projects!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re passionate about open-source projects and how your background makes you a perfect fit for our team at lowRISC. Keep it engaging and personal!
Showcase Your Projects: If you've worked on any open-source projects or have relevant experience, make sure to mention them in your application. We love seeing real-world examples of your work and how you’ve contributed to the community.
Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you don’t miss out on any important updates from our team!
How to prepare for a job interview at lowRISC
✨Know Your Stuff
Make sure you brush up on your SystemVerilog and UVM knowledge. Be ready to discuss specific projects where you've implemented verification tests, as this will show your hands-on experience and expertise.
✨Showcase Your Experience
With over 5 years in design verification, you’ll want to highlight key achievements from your past roles. Prepare examples that demonstrate your problem-solving skills and how you've contributed to open-source projects.
✨Ask Insightful Questions
Prepare thoughtful questions about lowRISC's current projects and their approach to open-source development. This shows your genuine interest in the company and helps you assess if it’s the right fit for you.
✨Be Ready for Technical Challenges
Expect some technical questions or challenges during the interview. Practise explaining your thought process clearly, as communication is key in engineering roles. Don’t hesitate to ask for clarification if needed!