A nonprofit technology organization in Cambridge is seeking a Senior DV Engineer to enhance verification standards for open source projects. The ideal candidate has over 5 years of experience in design verification, extensive knowledge of SystemVerilog and UVM, and a degree in a technical field. This role offers a competitive salary of £68,000–£88,000, benefits including a generous leave package, and opportunities for hybrid working after an initial probationary period. #J-18808-Ljbffr
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lowRISC CIC Recruiting Team