The Role
In this role you will have the opportunity to apply industrial‑strength design verification to high quality open source code bases. We are raising the bar for verification of open source projects to meet the highest commercial standards. Your focus will be on the verification of the range of open source designs including OpenTitan. Verification will be at both system and block level; blocks include RISC‑V cores, a separate special‑purpose CPU for cryptographic operations (OTBN), hardware accelerators for multiple cryptographic algorithms and a variety of peripherals (e.g. USB, I2C and SPI).
You Will
- Design, implement and debug block‑level and system‑level tests and testbenches using SystemVerilog and UVM.
- Stay up to date with the latest best practices and bring innovations to lowRISC.
- Develop test and coverage plans for new or updated silicon designs.
- Actively review contributions to our open source projects.
- Triage and debug nightly regressions.
- Contribute to the ongoing design and development of our test and continuous integration infrastructure.
- Collaborate with partners to turn their specifications into verification collateral that will lead to successful tapeouts.
Candidate Requirements
Essential
- 5 years+ prior industry experience of design verification including significant SystemVerilog and UVM usage.
- Experience across the full verification cycle from initial planning to final tape out.
- Confident in providing work estimates and coordinating work with a project manager.
- Comfortable working with engineers across multiple organisations in multidisciplinary teams.
- Familiarity with Git and code review using services such as GitHub.
- Programming using C and/or Python in tests and automation.
- Undergraduate degree in a technical discipline or equivalent experience.
Desirable
- Broad experience range with background across multiple types of hardware blocks.
- Understanding of security countermeasures against attacks such as fault injection or side‑channel analysis.
- Experience working with the RISC‑V ISA or other instruction sets.
- Formal verification with tools such as Jasper.
- Experience with silicon bring‑up, silicon debugging, and post‑silicon validation.
- Experience with leading a team or being a leading technical contributor.
Salary and Benefits
Salary dependent upon experience.
Benefits include:
- 25 days annual leave plus 8 bank holidays.
- 12.5% employer’s pension contribution (subject to employee salary sacrifice of 6%).
- 4 weeks paid sabbatical after 4 years service.
- Private Medical Insurance, Group Income Protection Insurance, Critical Illness Insurance, Life Insurance.
- The opportunity to attend appropriate industry conferences and/or training.
We are open to discussions about hybrid working after an initial probationary period.
We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity. If you need any adjustments made to the application or selection process, please let us know by emailing: hr@lowrisc.org
