Front-End Digital Design Engineer

The Front-End Digital Design Engineer will join a small dynamic team that aims to develop a novel memory technology. The engineer will work closely with the engineering team and undertake various engineering activities, providing the opportunity to make a significant impact. We are seeking a skilled and enthusiastic professional to focus on the design and development of digital circuits for a variety of applications. The role involves architectural definition, RTL implementation, and verification of complex digital IP and sub-systems, using standard design methodologies and EDA tools to ensure robust and high‑quality designs for our semiconductor products.

Key Responsibilities

• RTL Design and Development: Architect and implement high‑quality, synthesizable RTL (Register Transfer Level) code using industry‑standard Hardware Description Languages (HDLs) such as Verilog or SystemVerilog.
• System‑Level Design and Integration: Collaborate with architects and system engineers to define functional blocks, interfaces, and control logic, ensuring seamless integration into larger SoC architectures.
• Verification and Debugging: Participate in design verification activities, including testbench development using methodologies like UVM or constrained‑random stimulus generation, and formal verification techniques; also debug RTL and system‑level issues.
• Timing Closure and Signoff: Work closely with backend teams to ensure timing closure and perform static timing analysis (STA).
• Methodology and Tooling: Stay updated with the latest advancements in digital design methodologies and Electronic Design Automation (EDA) tools, adopting new approaches to enhance productivity and efficiency.
• Collaboration and Documentation: Work effectively in cross‑functional teams, contribute to technical reviews, and maintain comprehensive design documentation, including specifications, design reports, and test plans.

Job Requirements

• Bachelor’s or Master’s degree in Computer Science, Electrical & Electronic Engineering, Material Science, or related fields with 5+ years of directly relevant experience.
• Proven experience in front‑end digital IC design.
• Expertise in Verilog and SystemVerilog for RTL design and verification.
• Hands‑on experience with industry‑standard EDA tools for simulation and synthesis (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa).
• Good understanding of low‑power design techniques.
• Strong analytical and problem‑solving skills.
• Excellent communication and interpersonal skills, with the ability to work effectively in a team environment.
• Proficiency in scripting languages like Python or TCL for automation of design flows.
• Experience taking designs into production.
• Experience with memory interfaces (Flash, SRAM).
• Knowledge of standard interfaces such as AMBA protocols (APB, AHB, AXI, SPI, I2C).
• Exposure to formal verification techniques.
• Experience or desire to work in a start‑up environment.
• Ability to plan, coordinate, and take responsibility for effective and on‑time completion of project activities.
• Self‑motivated and creative with a passion for achieving success and excellence.

Company

LoMaRe Technologies is a semiconductor start‑up developing emerging non‑volatile memory (NVM) technologies with proprietary intellectual property. Headquartered in London, UK, LoMaRe is a spin‑off company from the world‑leading institution Imperial College London. Our ambition is to commercialise scientific innovation, and we are looking to add experienced experts to our London team to develop our memory technology.

To Apply

If you feel you are a suitable candidate and would like to work for LoMaRe Technologies, please do not hesitate to apply.