Application Specific Integrated Circuit Design Engineer in Glasgow

Kelvin Quantum is a Glasgow-based semiconductor company spun out of the University of Glasgow.

We develop advanced hardware solutions capable of continuous operation from room temperature to deep cryogenic environments, near absolute zero.

Our portfolio ranges from individual integrated circuits to fully integrated electronic systems for quantum control and readout, tailored to meet the requirements of next‑generation quantum technologies.

Our technologies let quantum hardware teams build scalable, stronger machines with real‑world impact.

The Role

As an ASIC Designer for Cryo‑CMOS, you will design low‑power, low‑noise integrated circuits (DACs, ADCs, LNAs, RF mixers, PLLs, multiplexers, power supplies, and bias networks) that must operate reliably at cryogenic temperatures.

You will own circuits end‑to‑end: architecture, specification, schematic, layout supervision, tape‑out, and characterisation in our cryogenic lab.

It is a hands‑on role with a clear route into technical leadership as we grow.

Key responsibilities

• Take analogue, mixed‑signal and RF CMOS blocks from specification to silicon, schematic, layout supervision, tape‑out, and bring‑up.
• Design low‑noise, low‑power circuits for the control and readout of various types of solid‑state qubits.
• Perform full design verification: schematic, pre‑ and post‑layout simulations.
• Collaborate with our packaging, PCB, FPGA, and quantum applications teams to integrate ASICs into cryostat subsystems.
• Support tape‑out, contribute to silicon characterisation at room and cryogenic temperatures, and prepare technical documentation.
• Mentor more junior engineers and help shape how the IC team works as we grow.
• What we are looking for
• A degree in Electrical/Electronic Engineering, Physics, Microelectronics, or a related field.
• At least 3 years of professional experience in analog, RF, or mixed‑signal CMOS IC design.
• Solid production experience with Cadence Virtuoso, Spectre, ADE, and a full ASIC flow including DRC/LVS, parasitic extraction, and post‑layout simulation (Calibre or PVS/QRC).
• A real design portfolio in at least one of: data converters (DAC/ADC), low‑noise amplifiers, RF mixers, RF synthesizers, band‑gap/biasing, or high‑speed multiplexers.
• A working knowledge of CMOS device physics, noise analysis, mismatch, and layout‑dependent effects.
• At least two ASICs successfully taken through tape‑out and bring‑up.
• Good written and verbal communication.
• Right to work in the UK.
• Nice to have
• Hands‑on experience designing or measuring ICs at cryogenic temperatures.
• Familiarity with cryogenic device modelling or cryo‑CMOS SPICE models.
• Experience with advanced CMOS nodes, 40 nm and below, 22/28 nm FDSOI.
• A background in IC design for quantum computing control and readout, or extreme environments.
• RF measurement and microwave packaging experience.
• Experience with cloud‑based EDA flows (AWS or equivalent) and foundry MPW / shuttle logistics.
• Experience with Verilog / System Verilog to talk sensibly with the FPGA and digital teams.
• Track record of publications, patents, and/or shipped products.

What we offer

• Salary £55,000 – £75,000 depending on experience.
• Performance‑led annual bonus.
• Pension scheme with enhanced employer contribution.
• 28 days’ annual leave plus UK public holidays.
• Annual learning and conference budget.
• A friendly office in Glasgow, with regular team socials and off‑sites.
• Equal opportunity

We’re committed to building a diverse and inclusive team and providing equal employment opportunity regardless of age, sex, sexual orientation, gender identity, race, colour, religion, disability status, marital status, pregnancy, gender reassignment, or any other protected characteristic.

If you need any adjustments during the application or interview, just let us know.

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