Kandou is seeking an Analog Layout Engineer (Lead) to drive custom analog layout and verification for high-speed SerDes and memory interfaces across 28nm to 7nm nodes. You will collaborate with design teams to implement robust layouts, ensure IP and chip integration, and engage with customers on requirements and IP delivery.
The role demands hands-on experience in analog layout and strong communication skills in a fast-paced semiconductor environment. EU/CH/UK location flexibility is offered.
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Lead Analog Layout Engineer for High-Speed AI Interconnects in Reading employer: Kandou AI
At Kandou, we pride ourselves on being an exceptional employer that fosters innovation and collaboration in the rapidly evolving field of AI infrastructure. Our dynamic work culture encourages creativity and offers ample opportunities for professional growth, while our commitment to reducing the Total Cost of Ownership for hardware systems positions us at the forefront of technological advancement. Located in the EU/CH/UK, we provide a supportive environment where employees can thrive and contribute to groundbreaking solutions that democratise AI.
