Firmware Lead in Cambridge

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

As Firmware Lead, you will lead implementation and delivery of real-time embedded firmware for Kandou's Randa 1.6T Active Electrical Cable platform. This is a coding-heavy technical leadership role: you will spend the majority of your time writing and reviewing C/C++, debugging firmware and hardware interactions, and supporting pre-silicon and post-silicon bring-up. You will turn the Firmware Architect's system design into production code, own implementation quality and delivery, and mentor engineers while remaining active in the codebase.

Open locations: India (Hyderabad or Bangalore), UK (Reading or Cambridge), Switzerland (Lausanne).

Responsibilities

• Lead the implementation and delivery of real-time embedded firmware for AEC retimer silicon across 224G/lane, 448G/lane and forward-looking 896G/lane configurations; remain a hands‑on C/C++ contributor.
• Implement and maintain boot, configuration, calibration, link‑training, fault‑recovery and run‑time supervision state machines on resource‑constrained RISC‑V or ARM platforms.
• Translate approved firmware architecture into module designs, APIs, task and interrupt models, memory budgets and hardware/software contracts; surface implementation tradeoffs early.
• Code, debug and optimize firmware for SerDes equalisation and adaptation, FEC‑aware monitoring and re‑adaptation, telemetry capture, thermal behaviour and power management.
• Own low‑level drivers and management interfaces including SPI, I2C/SMBus, I3C, MCTP and JTAG, and integrate firmware services with the CMIS management layer.
• Drive pre‑silicon development and first‑silicon bring‑up; isolate issues across firmware, RTL, boards and lab setups using JTAG, register traces and targeted instrumentation.
• Set coding and review standards; build unit, integration and hardware‑in‑loop tests; enforce CI, static analysis and release evidence; improve Python‑based build, debug and test tools.
• Break the roadmap into deliverable work packages, estimate and track execution, mentor firmware engineers and coordinate with architecture, ASIC, DV, validation, SI and applications teams.

Essential Experience

• 8+ years developing and debugging production real‑time firmware in C/C++, including 2+ years leading firmware modules, projects or a small team.
• Expert hands‑on C/C++ in resource‑constrained systems, with recent evidence of personal code delivery, code review and complex defect resolution.
• Firmware experience on a retimer, gearbox, PHY, AEC, AOC, optical module, networking ASIC or comparable high‑speed mixed hardware/software product.
• RISC‑V and/or ARM bare‑metal or RTOS firmware, including interrupts, traps, CSR or register access, concurrency and tight RAM/flash budgets.
• RTOS development with Zephyr, FreeRTOS or equivalent; ownership of scheduling, synchronization, timing and failure recovery.
• At least one silicon or board bring‑up cycle using JTAG and related debug mechanisms, with root‑cause analysis across firmware, drivers, RTL and hardware.
• Python, Git/GitLab, Make/CMake, CI, unit and integration testing, and static analysis, with disciplined reproducible development workflows.

BS in Electrical Engineering, Computer Engineering or Computer Science, or equivalent experience; strong communication, planning, mentoring and cross‑functional leadership.

Useful Experience

• IEEE 802.3ck or 802.3dj link training and equalisation, SerDes adaptation algorithms, channel‑quality monitoring and register‑level PHY tuning.
• FEC exposure including KP4 or RS‑544, pre‑FEC and post‑FEC telemetry, symbol‑error analysis and FEC‑aware recovery behaviour.
• CMIS 5.x firmware integration, module or datapath state machines, VDM telemetry, and sideband protocols including SMBus, I3C and MCTP.
• Bootloaders, secure boot, root of trust, authenticated A/B firmware updates, rollback protection and field‑recovery mechanisms.
• Pre‑silicon firmware development using QEMU, SystemC, FPGA, simulation or emulation; heterogeneous multicore or vector‑processing systems.

PCIe or CXL, hyperscaler qualification, interoperability debugging, and production support for field or manufacturing issues.

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