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For Companies At a Glance
- Tasks: Design and maintain testbenches for cutting-edge FPGA systems in a high-frequency trading environment.
- Company: Join a prestigious high-frequency trading company at the forefront of design verification innovation.
- Benefits: Competitive salary, dynamic work culture, and opportunities for professional growth.
- Why this job: Be part of a pioneering team and make a real impact in the world of technology.
- Qualifications: 2+ years in RTL functional verification with expertise in SystemVerilog, UVM, Python, or C++.
The predicted salary is between 36000 - 60000 £ per year.
We're working with one of the most prestigious high-frequency trading companies in the world to find a verification engineer to help verify their complex low-latency FPGA systems. You'll be joining a team at the forefront of innovation in design verification, where you'll be supported in pushing the envelope alongside top pioneers in verification.
Responsibilities
- Design and maintain robust testbenches and targeted tests using the organisation’s mixed open-source and proprietary verification environment.
- Develop and own comprehensive verification plans, ensuring coverage goals and test strategies are clear and defensible.
- Identify and diagnose RTL issues quickly, working directly with designers to accelerate bring-up and resolve design defects efficiently.
- Oversee and refine the test infrastructure, including management of test suites, CI pipelines, and the improvement of both internal and open-source tooling.
Requirements
- Strong debugging and analytical capability, able to isolate and resolve complex RTL and testbench issues efficiently.
- At least two years of professional RTL functional verification experience for FPGA or ASIC designs.
- Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis.
- Proficiency in Python and/or C++ for building verification infrastructure, tooling, and automation.
Design Verification Engineer - Platform Recruitment in London employer: Jobster
Contact Detail:
Jobster Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Design Verification Engineer - Platform Recruitment in London
✨Tip Number 1
Network like a pro! Reach out to folks in the industry, especially those already working at the company you're eyeing. A friendly chat can give you insider info and maybe even a referral!
✨Tip Number 2
Show off your skills! If you’ve got a portfolio or any projects that highlight your design verification expertise, make sure to share them during interviews. It’s a great way to demonstrate your hands-on experience.
✨Tip Number 3
Prepare for technical questions! Brush up on SystemVerilog, UVM, and your debugging techniques. Practising common interview questions can help you feel more confident and ready to impress.
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, we’re here to support you every step of the way!
We think you need these skills to ace Design Verification Engineer - Platform Recruitment in London
Some tips for your application 🫡
Tailor Your CV: Make sure your CV is tailored to the role of Design Verification Engineer. Highlight your experience with RTL functional verification, SystemVerilog, and UVM. We want to see how your skills match what we're looking for!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you're passionate about design verification and how your background makes you a great fit for our team. We love seeing enthusiasm and a personal touch!
Showcase Your Projects: If you've worked on any relevant projects, make sure to mention them in your application. Whether it's a complex FPGA design or a cool automation tool you built, we want to know what you've done and how it relates to the role.
Apply Through Our Website: We encourage you to apply through our website for a smoother process. It helps us keep track of applications and ensures you get all the updates directly from us. Plus, it’s super easy!
How to prepare for a job interview at Jobster
✨Know Your RTL Inside Out
Make sure you brush up on your RTL functional verification knowledge, especially around FPGA and ASIC designs. Be ready to discuss specific projects where you've debugged complex issues, as this will show your hands-on expertise.
✨Show Off Your Testbench Skills
Prepare to talk about your experience with SystemVerilog and UVM. Have examples ready of how you've designed and maintained testbenches, and be prepared to explain your approach to achieving coverage goals.
✨Demonstrate Your Problem-Solving Prowess
Expect questions that assess your analytical capabilities. Think of scenarios where you identified and resolved RTL issues quickly, and be ready to walk through your thought process during those challenges.
✨Get Comfortable with Python and C++
Since proficiency in Python and/or C++ is key for building verification infrastructure, be prepared to discuss any relevant projects. If you’ve automated processes or improved tooling, share those experiences to highlight your technical skills.
