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- Tasks: Join a top-tier trading company to verify cutting-edge FPGA systems and innovate in design verification.
- Company: Prestigious high-frequency trading firm known for its innovative culture.
- Benefits: Competitive salary, dynamic work environment, and opportunities for professional growth.
- Why this job: Be at the forefront of technology and make a real impact in the trading industry.
- Qualifications: 2+ years in RTL verification, strong debugging skills, and expertise in SystemVerilog and UVM.
- Other info: Collaborative team with a focus on pushing boundaries in verification technology.
The predicted salary is between 36000 - 60000 £ per year.
We're working with one of the most prestigious high-frequency trading companies in the world to find a verification engineer to help verify their complex low-latency FPGA systems. You'll be joining a team at the forefront of innovation in design verification, where you'll be supported in pushing the envelope alongside top pioneers in verification.
Responsibilities
- Design and maintain robust testbenches and targeted tests using the organisation’s mixed open-source and proprietary verification environment.
- Develop and own comprehensive verification plans, ensuring coverage goals and test strategies are clear and defensible.
- Identify and diagnose RTL issues quickly, working directly with designers to accelerate bring-up and resolve design defects efficiently.
- Oversee and refine the test infrastructure, including management of test suites, CI pipelines, and the improvement of both internal and open-source tooling.
Requirements
- Strong debugging and analytical capability, able to isolate and resolve complex RTL and testbench issues efficiently.
- At least two years of professional RTL functional verification experience for FPGA or ASIC designs.
- Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis.
- Proficiency in Python and/or C++ for building verification infrastructure, tooling, and automation.
Apply below for more information!
Design Verification Engineer - Platform Recruitment employer: Jobster
Contact Detail:
Jobster Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Design Verification Engineer - Platform Recruitment
✨Tip Number 1
Network like a pro! Reach out to folks in the industry, attend meetups, and connect with people on LinkedIn. You never know who might have the inside scoop on job openings or can refer you directly.
✨Tip Number 2
Show off your skills! Create a portfolio showcasing your best work in design verification. Include projects that highlight your expertise in SystemVerilog, UVM, and any cool automation tools you've built. This will make you stand out!
✨Tip Number 3
Prepare for interviews by brushing up on common technical questions related to RTL and testbenches. Practice explaining your thought process when debugging issues, as this is key for roles like the one we're hiring for.
✨Tip Number 4
Don't forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, we love seeing candidates who take the initiative to engage directly with us.
We think you need these skills to ace Design Verification Engineer - Platform Recruitment
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your experience with RTL functional verification and any relevant projects. We want to see how your skills align with the role, so don’t be shy about showcasing your expertise in SystemVerilog, UVM, and Python or C++.
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re passionate about design verification and how you can contribute to our team. Be specific about your achievements and how they relate to the responsibilities listed in the job description.
Show Off Your Problem-Solving Skills: In your application, give examples of how you've identified and resolved complex RTL issues in the past. We love seeing candidates who can think critically and act quickly, so share those success stories!
Apply Through Our Website: We encourage you to apply directly through our website for a smoother process. It helps us keep track of applications and ensures you get all the updates about your application status. Plus, it’s super easy!
How to prepare for a job interview at Jobster
✨Know Your Tools Inside Out
Make sure you’re well-versed in SystemVerilog, UVM, Python, and C++. Brush up on your debugging skills and be ready to discuss how you've used these tools in past projects. Being able to demonstrate your hands-on experience will really impress the interviewers.
✨Prepare for Technical Questions
Expect to face some challenging technical questions related to RTL verification and FPGA systems. Review common issues and solutions you've encountered in your work. Practising problem-solving scenarios can help you articulate your thought process clearly during the interview.
✨Showcase Your Verification Plans
Be prepared to discuss your approach to developing verification plans. Highlight any comprehensive strategies you've implemented in previous roles, focusing on how you ensured coverage goals were met. This shows that you understand the importance of a structured approach in verification.
✨Ask Insightful Questions
Interviews are a two-way street! Prepare thoughtful questions about the company’s verification environment and team dynamics. This not only shows your interest but also helps you gauge if the company is the right fit for you. Plus, it gives you a chance to engage with the interviewers on a deeper level.
