Lead Digital Verification Engineer

Lead Digital Verification Engineer position located in Edinburgh, Scotland. Reports to Design Engineering Group Director.

Job Overview

The Cadence Silicon Systems Group (SSG) develops leading‑edge intellectual property (IP) for a variety of high‑tech markets. As part of the Central Engineering Team, you will define and support the adoption of cutting‑edge verification tools and methodologies, focusing on AI and machine learning. The role requires working across multiple projects and teams to accelerate adoption of the latest verification best practices.

Responsibilities

• Develop and support the adoption of generative AI tools for creating and updating UVM and formal verification environments.
• Develop methodology guidance and end‑to‑end flows to ensure AI tools are used consistently, efficiently, and predictably.
• Develop and roll out solutions that reduce verification debug time.
• Automate documentation checks to improve quality and consistency.
• Build tools and processes to support verification planning.
• Optimize UVM regressions through improved automation and machine learning.
• Maintain and develop best practices for functional safety verification, gate‑level simulation, and low‑power verification.
• Maintain and improve design‑review checklists and quality documentation.

Qualifications

• Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline.
• 4+ years of experience in the microelectronics/EDA industry.
• Proficiency in SystemVerilog and assertions.
• Hands‑on experience with Metric‑Driven Verification (MDV).
• Strong knowledge of constrained‑random verification techniques (e.g., UVM).
• Excellent spoken and written English.
• Self‑motivated with strong planning, interpersonal, and communication skills.

Preferred Skills

• Formal verification experience and related applications.
• Proficiency with scripting languages (e.g., Python).
• Knowledge of AI agent development (tools, concepts, and infrastructure).
• Methodology development and change‑management experience.
• Familiarity with front‑end design tools (e.g., LINT, CDC analysis).
• Exposure to quality processes and standards (e.g., ISO 9001, ISO 26262).

Benefits

• Competitive salary.
• 25 days holiday per year.
• Private medical and dental plans, income protection and life insurance.
• Group personal pension plan.
• Cycle‑to‑work scheme and gym subsidy.
• 5 days paid time to volunteer.
• Employee stock purchase plan.

Travel

Less than 5% travel required.

Equal Employment Opportunity

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.