Hardware Engineer (FPGA/ASIC)

Hardware Engineer (FPGA/ASIC)

Full-Time 22500 - 27500 £ / year (est.) No working from home possible
Janestreet

At a Glance

  • Tasks: Collaborate on real-world hardware projects and learn cutting-edge programming techniques.
  • Company: Join Jane Street, a leader in innovative tech with a supportive culture.
  • Benefits: Gain hands-on experience, mentorship, and exposure to advanced tools in a dynamic environment.
  • Other info: Exciting opportunities for growth and development in a collaborative team.
  • Why this job: Make a real impact while learning from industry experts in hardware engineering.
  • Qualifications: Experience with hardware description languages and a passion for problem-solving.

The predicted salary is between 22500 - 27500 £ per year.

About the Position

Our goal is to give you a real sense of what it's like to work at Jane Street full time while also providing a truly unparalleled educational experience. As an intern, you are paired with full-time employees who act as mentors, collaborating with you on real-world projects we actually need done. In this internship, you'll learn how we use tools to make programming faster, more pleasant, and more reliable. We apply these same principles to our hardware engineering work, and we're looking for people who are interested in using programming language technology to improve the process of designing, testing, and validating hardware designs.

We use Hardcaml, an OCaml library for succinctly describing hardware in RTL. Hardcaml is tightly integrated into our development environment, so you'll also gain lots of exposure to the libraries and tools that are foundational to our internal systems. No previous knowledge of Hardcaml is required. The hardware team at Jane Street works on both FPGA and ASIC designs. Depending on your background and experience, we'll craft a project that gives you exposure to our shared Hardcaml tech stack, as well as targeting an FPGA or ASIC platform. During the program, you'll dive deep on one project, mentored closely by the full-time employees who helped design it. Some intern projects consider big-picture questions that we're still trying to figure out, while others involve building something new. Your mentors will help you gain a better understanding of the wide range of problems we solve every day.

We expect interns to build hardware applications from concept to a working design; your projects will predominantly involve OCaml & Hardcaml, for both RTL design and testing/integration.

About You

We don't expect you to have a background in finance, OCaml, functional programming, or any other specific field— we're looking for smart people who enjoy solving interesting problems. We're more interested in how you think and learn than what you currently know. You should be:

  • Comfortable with a software programming language
  • Experienced with a Hardware Description (or Construction) language (VHDL, Verilog, Chisel, Pymtl, or other), for both writing and testing hardware designs
  • Experienced working with FPGA or ASIC vendor tools - Vivado or Quartus for FPGAs, Genus or Innovus for ASICs
  • Experienced with building a working hardware project (either FPGA or ASIC) through an academic, professional, or personal project
  • Interested in learning how to use FPGAs or ASICs in the context of networking
  • Fluent in English

Hardware Engineer (FPGA/ASIC) employer: Janestreet

Jane Street is an exceptional employer located in Greater London, offering a dynamic work culture that fosters collaboration and innovation. Employees benefit from engaging projects in finance tech, opportunities for professional growth, and a commitment to using cutting-edge technology. With a focus on intellectual curiosity and teamwork, Jane Street provides a rewarding environment for those passionate about software engineering.

Janestreet

Contact Details:

Janestreet Recruitment Team

We think you need these skills to ace Hardware Engineer (FPGA/ASIC)

OCaml
Hardcaml
Hardware Description Language (VHDL, Verilog, Chisel, Pymtl)
FPGA Design
ASIC Design
Vivado
Quartus