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- Tasks: Design, test, and deploy advanced hardware in a collaborative team.
- Company: Innovative tech firm focused on ultra-low latency solutions.
- Benefits: Competitive salary, flexible working, and opportunities for professional growth.
- Other info: Dynamic environment with a focus on innovative tools and career advancement.
- Why this job: Join a small team and make a real impact on cutting-edge hardware projects.
- Qualifications: Experience in physical design and RTL, with a collaborative mindset.
The predicted salary is between 60000 - 80000 £ per year.
About the Position
We are looking to hire an ASIC Physical Design Engineer to help us design, test and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. This isn't a traditional PD role. We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and reason about design decisions that cross the front-end/back-end boundary. If you've spent your career exclusively in PD, this probably isn't the right fit-but if you've worked across the stack, either because you started as an RTL designer and moved into PD, or because you were on a smaller team where you had to wear multiple hats, we'd love to talk.
We're big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That's why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don't expect you to know OCaml (we'll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.
About You
- You have hands-on experience building and running modern physical design flows (e.g., floorplanning, place and route, timing closure, physical verification, power analysis).
- You don't need to have optimised every last detail of every flow, but you should have broad enough experience across PD that you can own a flow end-to-end and know where the risks are.
- Beyond PD, you can read and write RTL and understand how front-end design decisions affect physical implementation-and vice versa.
ASIC Physical Design Engineer | London, UK employer: Jane Street
Contact Detail:
Jane Street Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land ASIC Physical Design Engineer | London, UK
✨Tip Number 1
Network like a pro! Reach out to your connections in the ASIC and hardware engineering space. Attend meetups, webinars, or even casual coffee chats. You never know who might have the inside scoop on job openings or can refer you directly.
✨Tip Number 2
Show off your skills! Create a portfolio showcasing your projects, especially those that highlight your experience across the chip design process. This will give potential employers a tangible sense of what you can bring to the table.
✨Tip Number 3
Prepare for interviews by brushing up on both physical design and RTL concepts. Be ready to discuss how your past experiences have shaped your understanding of the entire design flow. We want to see your thought process and how you tackle challenges!
✨Tip Number 4
Don't forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, it shows you're genuinely interested in joining our team and contributing to our innovative projects.
We think you need these skills to ace ASIC Physical Design Engineer | London, UK
Some tips for your application 🫡
Show Your Unique Journey: We want to see how your experience has shaped you as an ASIC Physical Design Engineer. Don’t just list your skills; tell us about the projects you've worked on and how you've worn multiple hats in your career. This helps us understand your journey and how you think across the stack.
Tailor Your Application: Make sure to customise your application for this role. Highlight your hands-on experience with physical design flows and your ability to read and write RTL. We love seeing candidates who can connect the dots between front-end and back-end design, so make that clear!
Be Genuine and Enthusiastic: Let your passion for hardware engineering shine through! We’re looking for engineers who are excited about using better tools to enhance productivity and joy in their work. Share why you’re interested in our team and what excites you about the role.
Apply Through Our Website: Don’t forget to submit your application through our website! It’s the best way for us to receive your details and ensures you’re considered for the role. Plus, it gives you a chance to explore more about us and what we do at StudySmarter.
How to prepare for a job interview at Jane Street
✨Know Your PD Flows
Make sure you brush up on your knowledge of modern physical design flows like floorplanning, place and route, and timing closure. Be ready to discuss your hands-on experience with these processes and how you've managed risks in previous projects.
✨Show Your Versatility
Since this role isn't just about physical design, highlight any experience you have with RTL design. Be prepared to explain how your understanding of front-end decisions impacts physical implementation, and vice versa. This will show that you can think across the entire chip design process.
✨Embrace New Tools
The company values engineers who are excited about using better tools to enhance productivity. Familiarise yourself with Hardcaml or similar toolchains, and be ready to discuss how you've leveraged tools in your past work to improve outcomes.
✨Be Ready for Collaboration
This role involves working closely with teams across trading, networking, and research infrastructure. Prepare examples of how you've successfully collaborated with cross-functional teams in the past, and demonstrate your ability to communicate effectively with different stakeholders.