Description:
- Strong hands-on experience in digital design verification using System Verilog and UVM.
- Experience working with existing UVM testbenches, including modifying, extending, and debugging reusable verification components.
- Good understanding of constrained-random verification, functional coverage, assertions, scoreboards, and checkers.
- Experience in subsystem-level or SoC-level functional verification.
- Strong understanding of SoC architectures, bus protocols, register interfaces, and processor-controlled peripherals.
- Experience developing, executing, or debugging embedded C tests for processor-based SoC verification.
- Ability to debug complex RTL simulation failures using industry-standard simulators and waveform debugging tools.
- Experience executing regressions, analyzing failures, and driving functional coverage closure.
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System Design Verification Engineer in Cambridge employer: iXceed Solutions
As a Microsoft Power Platform CoPilot Architect, you will thrive in a dynamic and innovative environment located in the heart of London. Our company prioritises employee growth through continuous learning opportunities and a collaborative work culture that values creativity and teamwork. With a hybrid work model, we offer flexibility while ensuring our team members are supported and engaged in meaningful projects that drive technological advancement.
