Digital Architect/FPGA Systems - UNB032 in Reading

Who are we? We hire those that seek to innovate across people, process and technology. Join our global workforce, visualise the future and strive for success. Our engineering campus and corporate offices in the UK and US are optimal environments for ideas and innovation to flourish.

ALL.SPACE has developed a smart terminal, capable of linking with all satellites, all networks, in all orbits, all at once. Our ground‐breaking software‐defined service enablement platform integrates intelligent routing, edge computing and on‐demand services to deliver unprecedented network resilience and application performance. Our terminal designs operate as fully electronic beam steering systems. Our IP has applications across a wide range of market sectors including aeronautical, land mobile, maritime, and 5G. It provides broadband, multi‐beam, two‐way communications with dynamic tracking of geostationary and non‐geostationary satellites or terrestrial nodes.

We are looking for world class talent to join our high‐performing team working on cutting edge technology in the satellite communications industry. We stand by our company values; INTEGRITY, INNOVATION & EXECUTION EXCELLENCE – giving you the opportunity to build your career in an environment where we encourage crisp decision‐making, challenging the status‐quo, championing your beliefs and ideas, sharing successes (and learning from failures) and working collaboratively with your fellow team members.

ALL.SPACE is committed to practicing and promoting diversity, inclusion and equality in the workplace. We aim to lead by example by making satellite communications a more inviting and accessible industry for all.

We are seeking a High‐Speed Digital Architect / FPGA Systems Engineer to lead the design of advanced distributed digital architectures for next‐generation satellite communication terminals. The role combines FPGA‐based digital beamforming design with high‐speed electrical engineering expertise, ensuring optimal system partitioning between FPGA logic and high‐speed interconnects (e.g., JESD204B/C, PCIe, Ethernet). This position will play a key role in defining the architecture, clock distribution, and data movement strategies that underpin high‐performance, scalable phased array platforms.

Responsibilities

• Define and implement distributed FPGA architectures for digital beamforming, balancing algorithmic partitioning, inter‐FPGA communication, and JESD interface capabilities.
• Architect and design high‐speed digital PCBs using the latest FPGAs, ADCs, DACs, and SerDes interconnects.
• Design and optimize clock distribution networks and digital timing strategies for system‐wide synchronization.
• Perform signal integrity (SI) and power integrity (PI) analysis to ensure robust operation under challenging conditions.
• Collaborate with RF, antenna, and system engineers to enable seamless RF/digital co‐design for phased array terminals.
• Support hardware bring‐up, debug, and validation with oscilloscopes, logic analyzers, and high‐speed test equipment.
• Contribute to system‐level trade‐offs, ensuring FPGA logic structures and board architectures deliver optimal performance.
• Provide documentation, participate in design reviews, and support integration of hardware, firmware, and software.

Qualifications

• Master's degree (MSc, MEng) or Ph.D. in Electrical/Electronic Engineering, Computer Engineering, or a related discipline.
• Extensive hands‐on experience in FPGA design and implementation (Xilinx/AMD, Intel, or similar), including RTL development, timing closure, and simulation.
• Proven experience in implementing and integrating JESD204B/C blocks (transmit/receive) within FPGA designs, including link bring‐up, lane alignment, and deterministic latency handling.
• Strong understanding of distributed multi‐FPGA architectures, with expertise in synchronisation strategies (clock distribution, SYSREF/LMFC alignment, deterministic latency, inter‐FPGA communication).
• Deep knowledge of high‐speed digital design: SerDes, SI/PI, clocking, board layout for multi‐GHz interfaces.
• Experience with schematic capture and PCB design tools (Altium preferred) and the full hardware lifecycle.
• Solid lab skills for bring‐up, debug, and validation of FPGA designs and high‐speed digital hardware (using logic analyzers, BERTs, high‐speed oscilloscopes).

Desired Skills

• Experience designing distributed multi‐FPGA systems for high‐bandwidth applications (beamforming, HPC, etc.)
• Familiarity with SI/PI simulation tools (HyperLynx, Ansys, Keysight ADS, etc.).
• Exposure to RF system design considerations and integration of mixed‐signal components.
• Understanding of regulatory/reliability requirements (EMC/EMI, thermal, SWaP constraints).
• Knowledge of digital beamforming concepts and signal processing chains.
• Familiarity with the development of very low skew / low jitter clock distribution networks.

Benefits

• Stock Options
• Contributory Pension Scheme 3% standard
• 25 days Annual Leave + Public Holidays
• Cycle‐to‐Work Scheme
• Car Scheme (Salary Sacrifice)
• Free On‐Site Gym
• Employee Assistance Programs
• Discounts Platform