Senior Staff Analog Mixed-Signal Design and Modelling Engineer in Oxford

About IonQ: IonQ, Inc. is the world’s leading quantum platform and merchant supplier - delivering integrated quantum solutions across computing, networking, sensing, and security. IonQ’s newest generation of quantum computers, the IonQ Tempo, is the latest in a line of cutting-edge systems that have been helping customers and partners including Amazon Web Services and AstraZeneca achieve 20x performance results and accelerate innovation in drug discovery, materials science, financial modeling, logistics, cybersecurity, and defense. In 2025, the company achieved 99.99% two-qubit gate fidelity, setting a world record in quantum computing performance.

Location: This role is based at our Oxford, England (UK) office, with the option to work a few days a week remotely. Travel: Up to 5%.

Role: We are looking for a Staff Analog Mixed-Signal Design and Verification Engineer to join our Cryo-CMOS IC team at IonQ Oxford. In this role, you will design analog and mixed-signal blocks from specification through circuit design, simulation, layout, tape-out and silicon validation. You will also own top-level chip integration and modelling as a first-class part of our Cryo-CMOS development flow.

Responsibilities:

• Own the full-chip modelling strategy: model architecture, abstraction levels, accuracy targets and sign-off criteria used across the IC development flow.
• Own analog and mixed-signal blocks (references, DACs, switches, regulators, clock distribution) from specification through schematic design.
• Own top-level integration: define block interfaces and specifications, assemble the top level, and run the full-chip mixed-signal simulations that verify the ASIC.
• Develop Verilog-A and Verilog-AMS models of analog blocks and assemble them into a simulatable full chip.
• Build real-number models so the full chip runs in digital verification and regression at practical speed.
• Derive models from mathematics: turn a transfer function, a Z-parameter network description or a MATLAB analysis into robust Verilog-A with well-behaved tolerances.
• Define and run model-versus-schematic correlation, keeping models in sync with design releases, and feed measured silicon behaviour back into the models and the block designs.
• Stand up mixed-signal co-simulation and regression (Cadence AMS Designer, Xcelium with Spectre).
• Lead block-level design reviews and mentor engineers on circuit design and modelling craft.

Requirements: To be successful, you will need deep analog and mixed-signal design and modelling experience, typically 10+ years. You will have designed blocks proven in silicon and models used in production tape-out flows. You will bring expert transistor-level design of precision analog blocks (references, DACs, regulators, switches, clock distribution) taken through PVT and Monte Carlo, layout and silicon validation, together with expert Verilog-A and Verilog-AMS and strong real-number modelling.

We're looking for someone who can design a block to specification and model it at the right fidelity, derive a model from equations and implement it end to end. You should be able to judge what to model and at what abstraction, align designers, verification and systems engineers on what a model does and does not promise, and contribute effectively within a fast-moving, highly technical team.

At IonQ, we believe in fair treatment, access, opportunity, and advancement for all while striving to identify and eliminate barriers. We empower employees to thrive by fostering a culture of autonomy, productivity, and respect. We are dedicated to creating an environment where individuals can feel welcomed, respected, supported, and valued. We are committed to equity and justice. We welcome different voices and viewpoints and do not discriminate on the basis of race, religion, ancestry, physical and/or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, transgender status, age, sexual orientation, military or veteran status, or any other basis protected by law. We are proud to be an Equal Employment Opportunity employer.